Wafer Level Package With Die Receiving Through-Hole
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Solution Overview
Problem
Conventional wafer level packaging techniques face issues with CTE mismatching between materials, leading to mechanical instability and increased manufacturing costs, and struggle to reduce device size due to thickness and complexity in the packaging process.
Innovation Solution
A fan-out wafer level packaging structure with a substrate having die receiving through-holes, an elastic core paste filling the gap between the die and substrate, a dielectric layer, a redistribution layer made from Ti/Cu/Au alloy, and terminal pads, which matches the CTE of the motherboard to absorb thermal mechanical stress and reduce package thickness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional WLP uses silicon die encapsulated by molding compound, then the die is protected and supported, but CTE mismatching causes mechanical instability and chip location shift during temperature cycling
Solution Approach 1:
The patent changes the material parameter of the substrate from conventional molding compound to a material with CTE matched to silicon die (such as ceramic or metal substrate with CTE between 3-7 ppm/°C). This parameter change eliminates CTE mismatching and prevents chip location shift during temperature cycling, thereby improving mechanical stability and reliability.
Solution Approach 2:
The patent employs a composite structure where the silicon die is mounted on a specialized substrate (ceramic or metal) that is then encapsulated by molding compound. This composite approach allows the substrate to provide CTE matching while the molding compound provides protection and support, resolving the contradiction between mechanical stability and CTE matching.
2Device complexity
If die are directly formed on the upper surface of the substrate, then the packaging process is simplified, but the build up layer increases the package thickness
Solution Approach 1:
The patent transitions from direct surface mounting to through-hole mounting, utilizing the vertical dimension (through the substrate thickness) to embed the die. This dimensional change allows the die to be positioned within the substrate rather than on the surface, reducing the overall package thickness while maintaining process simplicity.
Solution Approach 2:
The die is nested within the substrate by mounting it on the lower surface and filling the through-hole cavity with epoxy material. This nesting approach integrates the die into the substrate structure, eliminating the need for additional build-up layers and reducing package thickness.
3Ease of manufacture
If conventional package techniques divide dice on wafer into respective dies and package them respectively, then each die can be individually processed, but the manufacturing process becomes time consuming
Solution Approach 1:
The patent merges multiple individual die packaging operations into a single wafer-level process. The entire wafer is processed as one unit with through-holes formed and die mounted in bulk, then singulated after packaging. This combining of operations dramatically increases manufacturing productivity while still allowing individual die to be processed through the common wafer-level steps.
Solution Approach 2:
The through-holes are formed in the substrate before die mounting, and the entire wafer is packaged before singulation. This preliminary preparation of the substrate structure enables high-speed bulk processing of multiple dies simultaneously, improving manufacturing speed while maintaining flexibility for individual die processing needs.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides improved reliability and reduced device size with better CTE matching, eliminating thermal stress and manufacturing complexities, and simplifies the packaging process while maintaining electrical properties.
Implementation Method 1
the CTE difference (mismatching) between the materials of a structure of WLP and the mother board (PCB) becomes another critical factor to mechanical instability of the structure
Implementation Method 2
an elastic core paste materials filling into the space between die edge and side wall of die receiving through hole of said substrate
Data Source
AI summary
The present invention discloses a structure of package comprising: a substrate with a die receiving through hole; a base attached on a lower surface of the substrate; a die disposed within the die receiving through hole and attached on the base; a dielectric layer formed on the die and the substrate; a re-distribution layer (RDL) formed on the dielectric layer and coupled to the die; a protection layer formed over the RDL; and pluralities of pads formed on the protection layer and coupled to the RDL. The RDL is made from an alloy comprising Ti/Cu/Au alloy or Ti/Cu/Ni/Au alloy.