Wafer-Level Semiconductor Package With Through-Mold Vias for Fast Switching

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Solution Overview

Problem

Conventional semiconductor packages face limitations in heat dissipation and switching speed due to lead frame-based designs and wire bonds, which lead to parasitic effects and restricted customization, affecting performance in high-power applications.

Innovation Solution

The semiconductor package employs a wafer level packaging approach without lead frames or wire bonds, featuring an insulating portion and through-mold vias for connections, allowing topside cooling and customized form factors, reducing parasitic resistances and inductances.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If lead frame-based designs and wire bonds are used, then conventional semiconductor packages can be manufactured, but parasitic effects increase and switching speed decreases

Engineering Contradiction:

Improveswitching speedVSAvoidparasitic effects

Core Design Contradiction:

SpeedVSObject-generated harmful factors

Solution Approach 1:

The patent removes lead frames and wire bonds from the semiconductor package structure. By extracting these traditional interconnection elements, the design eliminates the parasitic inductances and resistances they introduce, directly improving switching speed and reducing harmful parasitic effects in high-power applications

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent transitions from traditional lateral wire bond connections to vertical through-mold vias that extend through the insulating portion. This dimensional change from surface-level connections to through-substrate connections shortens current paths and reduces parasitic effects, enabling faster switching speeds

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Temperature

If lead frame-based designs are used, then conventional packaging can be implemented, but heat dissipation performance is limited

Engineering Contradiction:

Improveheat dissipationVSAvoidpackage structure

Core Design Contradiction:

TemperatureVSDevice complexity

Solution Approach 1:

The patent removes the lead frame structure entirely and replaces it with a submount and through-mold via configuration. This extraction of the traditional heat dissipation pathway (lead frames) allows for alternative thermal management approaches, such as direct attachment of semiconductor devices to the submount for improved heat sinking

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent employs an insulating portion made of molded compound material that provides both electrical insulation and structural support. This composite material approach allows for integrated thermal management solutions while maintaining electrical isolation, improving heat dissipation without excessive structural complexity

Inventive Principle:

Principle #40Composite materials

3Object-generated harmful factors

If wafer level packaging without lead frames is used, then parasitic effects are reduced, but manufacturing process complexity increases

Engineering Contradiction:

Improveparasitic resistances and inductancesVSAvoidmanufacturing process

Core Design Contradiction:

Object-generated harmful factorsVSEase of manufacture

Solution Approach 1:

The patent forms through-mold vias through the insulating portion during the molding process itself, before final assembly. This preliminary action of creating connection pathways during the insulating portion formation step simplifies subsequent assembly operations and reduces overall manufacturing complexity despite the advanced packaging approach

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent combines multiple functions into integrated structures: the submount provides both mechanical support and electrical connection, while the insulating portion with embedded through-mold vias provides both insulation and interconnection. This merging of functions reduces the number of discrete components and assembly steps, easing manufacturing

Inventive Principle:

Principle #5Merging (Combining)

4Adaptability or versatility

If conventional package designs are used, then standardization is maintained, but customization for individual die sizes is restricted

Engineering Contradiction:

Improvecustomization for die sizesVSAvoidcost

Core Design Contradiction:

Adaptability or versatilityVSQuantity of substance

Solution Approach 1:

The patent enables customization by allowing the insulating portion dimensions, submount size, and through-mold via configuration to be adjusted based on the specific semiconductor die being packaged. This parameter flexibility allows optimal package design for each die size without requiring completely different package types, balancing customization with cost efficiency

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS20240421029A1Semiconductor Package

Publication Date: 2024.12.19 WOLFSPEED INC

AI summary

Semiconductor packages are provided. In one example, a semiconductor package includes a submount having a first surface and a second surface opposing the first surface. The semiconductor package includes at least one semiconductor die attached to the second surface of submount. The semiconductor package includes an insulating portion on the second surface of the submount and on the at least one semiconductor die. The insulating portion forms a first external surface of the semiconductor package. The semiconductor package includes at least one through-mold via extending from the first external surface through the insulating portion to at least one of the semiconductor die or the submount.