Wafer-Level IC Package Top Bottom Electrical Connections
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Wafer-level Chip Scale package (WLCSP) techniques lack top-to-bottom electrical connections, making them unsuitable for device stacking and certain sensor applications due to the absence of connection pads on the bottom side of the IC wafer, and require complex and costly Through-Silicon-Via (TSV) processing.
Innovation Solution
A wafer-level, batch-processed IC package with both top and bottom side electrical connections is achieved by forming trenches in the wafer at scribe regions and routing bonding wires through these trenches to connect the top and bottom sides, allowing for standard wire bonding technology and eliminating the need for complex TSV processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If Through-Silicon-Via (TSV) processing is used to achieve top-to-bottom electrical connections, then electrical connectivity between top and bottom sides is improved, but device complexity and manufacturing cost increase significantly
Solution Approach 1:
The patent introduces an intermediary structure (trench filled with conductive material) within the scribe region to achieve electrical connection between top and bottom sides. This intermediary approach avoids the complexity of TSV by using a simpler trench structure that can be filled with conductive paste or other conductive materials, thereby reducing manufacturing complexity while maintaining electrical connectivity.
Solution Approach 2:
The patent extracts the electrical connection function from the active circuit area and relocates it to the scribe region. By forming trenches specifically in the scribe region and filling them with conductive material, the connection function is separated from the complex circuit fabrication process, thereby reducing overall device complexity while achieving the required electrical connectivity.
2Reliability
If I/O pads are placed on the top side of the wafer, then electrical connections are achieved, but sensor applications are blocked due to physical obstruction of sensor elements
Solution Approach 1:
The patent moves the electrical connection interface from the top surface (two-dimensional plane) to the vertical dimension by creating through-silicon vias or trenches that extend from the top surface through to the bottom surface. This allows electrical connections to be made on both top and bottom surfaces simultaneously, enabling sensor elements on the top surface to remain unobstructed while maintaining electrical connectivity through the vertical dimension.
Solution Approach 2:
The patent segments the electrical connection function into multiple independent pads distributed across both top and bottom surfaces of the wafer. Instead of requiring large I/O pads on the top surface that would block sensor elements, the connection function is divided into multiple smaller pads located on both surfaces, allowing sensor elements to occupy the top surface area while electrical connections are established through the segmented pad structure.
3Productivity
If wire-bond pads are designed with small geometry for standard IC packaging, then integration density is improved, but WLCSP solder ball formation becomes infeasible due to insufficient space
Solution Approach 1:
The patent utilizes the vertical dimension by forming trenches or vias that extend through the substrate thickness. This allows wire-bond pads to maintain their small geometry for high integration density on the top surface, while the vertical trench structure provides additional space and structural support for solder ball formation, effectively adding a third dimension to the pad structure that accommodates both requirements.
Solution Approach 2:
The patent implements a nested structure where the conductive trench or via is formed within the substrate, and solder balls are placed within or adjacent to these trenches. This nesting approach allows the small wire-bond pads on the top surface to remain compact for high density, while the nested trench structure provides the necessary volume and structural support for solder ball attachment, enabling both small pad geometry and solder ball formation.
Data Source
AI summary
A wafer-level, batch processed, die-sized integrated circuit (IC) package with both top and bottom side electrical connections is disclosed. In one aspect, a number of bonding wires can be attached to bond pads on the top side (active circuit side) of an IC wafer. Trenches can be formed in the wafer at scribe regions and the bonding wires can extend through the trench. The trench can be filled with coating material. The bonding wires can be partially exposed on the top and/or bottom sides of the wafer to distribute electrical connections from the bond pads to the top and/or bottom sides of the wafer.