Wafer-Level Semiconductor Package Warpage Control
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Solution Overview
Problem
Wafer level semiconductor packaging faces issues with warpage due to thermal and mechanical stress, leading to compatibility problems in packaging processes and reduced durability of semiconductor packages, especially in larger sizes.
Innovation Solution
The implementation of a warpage control barrier line with a different modulus of elasticity than the molding layer, which partitions the molding layer into regions to distribute stress and reduce warpage, combined with a stepped structure at the edge of the semiconductor chip to increase the contact area with the molding layer for enhanced mechanical strength.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a large sized molding layer is formed at wafer level, then packaging effectiveness is improved, but warpage is generated due to CTE difference and stress
Solution Approach 1:
The molding layer is segmented into multiple regions by forming scribe lanes that divide the wafer into individual package units. This segmentation allows stress to be distributed across multiple smaller regions rather than concentrated in one large molding layer, thereby reducing overall wafer warpage while maintaining packaging effectiveness
Solution Approach 2:
Different regions of the wafer are treated differently by forming scribe lanes at specific locations (between adjacent packages) where stress concentration occurs. This local modification of the molding layer structure addresses warpage at critical stress points without affecting the overall packaging effectiveness of the wafer-level process
2Volume of moving object
If package size is reduced, then chip-size package is achieved, but crack and flaking at interface increases
Solution Approach 1:
Scribe lanes are formed in advance during the wafer-level packaging process, before the packages are separated. This preliminary action of creating stress-relief structures at the interface regions prevents crack and flaking from developing later, ensuring interface durability even in miniaturized chip-size packages
Solution Approach 2:
The scribe lanes act as intermediary structures at the interface between adjacent packages and the molding layer. These lanes serve as stress-relief zones that mediate the mechanical stress between different materials, preventing direct stress transmission that would cause crack and flaking at the package interfaces
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively disperses stress at the interface between the semiconductor chip and the molding layer, reducing warpage and improving the durability and reliability of the semiconductor package, enabling the fabrication of light, thin, short, and small packages without wafer warpage.
Implementation Method 1
a warpage control barrier line on the first semiconductor chip, said warpage control barrier line being arranged at the outside of the second semiconductor chip; wherein the warpage control barrier line and the molding layer have different modulus of elasticity with each other
Implementation Method 2
the warpage control barrier line and the molding layer have different modulus of elasticity with each other
Implementation Method 3
a stepped structure at the edge of the semiconductor chip to increase the contact area with the molding layer for enhanced mechanical strength
Data Source
AI summary
A wafer level semiconductor package is provided. A warpage control barrier line formed in every package of a single wafer prevents wafer from warping. The changed shape of the interface between a semiconductor chip and a molding layer at the edge of the package disperses stress applied to the outside of the package, and suppress the generation and propagation of crack. The size of the package is reduced to that of the semiconductor, and the thickness of the package is minimized.