Wafer Level Package Device Using Carrier Wafer for Warpage Control
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Solution Overview
Problem
Current semiconductor packages, such as DFN and QFN, face challenges in achieving smaller, thinner, and cooler designs while maintaining high production rates and thermal performance, particularly in lead-less configurations where the exposed die-attach-pad is essential for heat dissipation.
Innovation Solution
The formation of a wafer level package device involves creating a wafer level lead frame on a carrier wafer with similar thermal expansion coefficients to an active semiconductor wafer, allowing for electrical connection, subsequent removal of the carrier wafer, and formation of connectors like solder pads or conductive pillars, enabling the creation of singulated DFN or QFN chip packages with improved thermal performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a wafer level lead frame is formed on a carrier wafer with different thermal expansion coefficients, then the manufacturing process can proceed, but warpage occurs during thermal processing
Solution Approach 1:
The patent applies homogeneity by selecting a carrier wafer made of the same material as the active semiconductor wafer, ensuring identical thermal expansion coefficients. This material homogeneity prevents differential expansion during thermal processing, eliminating warpage issues while maintaining ease of manufacture through standardized material selection.
2Temperature
If the carrier wafer is retained in the final package, then structural support is provided, but the exposed die-attach-pad cannot be accessed for heat dissipation
Solution Approach 1:
The patent applies the extraction principle by removing the carrier wafer from the final package structure after it has served its purpose as a manufacturing substrate. This extraction allows the die-attach-pad to be exposed and accessible on the package bottom for direct heat dissipation to the PCB, while the carrier wafer's temporary structural support function is fulfilled during the assembly process.
3Strength
If tie-bar constructions are used to connect the lead frame, then mechanical strength is provided, but the package size and thickness increase
Solution Approach 1:
The patent applies extraction by eliminating the tie-bar construction entirely. The carrier wafer itself serves as the structural substrate that provides mechanical strength and support for the lead frame during assembly, replacing the need for separate tie-bar components. This removal of unnecessary elements reduces package size and thickness while maintaining required mechanical strength.
Solution Approach 2:
The carrier wafer performs multiple functions: it serves as the manufacturing substrate for forming the lead frame, provides mechanical support during assembly, and acts as a temporary structural element that is later removed. This multi-functionality eliminates the need for separate tie-bar components, reducing overall package complexity and size.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the production of small form-factor, high-efficiency chip scale packages with reduced warpage and manufacturing lead time, suitable for applications like power electronics, by leveraging similar thermal expansion coefficients and eliminating the need for tie-bar constructions.
Implementation Method 1
The carrier wafer and the active semiconductor wafer have at least substantially the same coefficients of thermal expansion
Data Source
AI summary
Techniques for forming a wafer level package device are disclosed. In one or more embodiments, the techniques include forming a wafer level lead frame on a carrier wafer and electrically connecting the wafer level lead frame to an active semiconductor wafer. The carrier wafer and the active semiconductor wafer have at least substantially the same coefficients of thermal expansion. The carrier wafer can be removed from the wafer level package device, and a number of connectors can be formed on the wafer level package device. The wafer level package device can be singulated to form chip packages, such as DFN or QFN packages.