Wafer-Level Semiconductor Packaging with Porous Aerogel

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Solution Overview

Problem

Traditional wafer-level packaging methods are complex, costly, and lack flexibility in creating small cavities that effectively protect active devices and individual passive components, often compromising mechanical and environmental protection due to high temperature requirements, adhesive outgassing, and the need for precise alignment.

Innovation Solution

A method involving a lithographically processable dielectric layer with device and contact pad openings, followed by deposition of a porous aerogel material, which is then covered with a second dielectric layer, allowing for precise exposure and protection of semiconductor devices with reduced stress and improved alignment tolerances.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If wafer bonding is used to create hermetic packages, then environmental protection is improved, but process complexity and manufacturing cost increase due to high temperature requirements and alignment precision

Engineering Contradiction:
Improveenvironmental protectionVSAvoidprocess complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent changes the bonding temperature parameter from high temperature (400°C+) to low temperature (room temperature or slightly elevated), enabling hermetic sealing without the complexity of high-temperature equipment and process control. This is achieved through the unique properties of the glass frit material that becomes viscous and flowable at elevated temperatures to form hermetic seals, then solidifies upon cooling.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent introduces glass frit as an intermediary material between the semiconductor wafer and the package substrate. This glass frit layer acts as a low-temperature bonding agent that flows to fill gaps and form hermetic seals, replacing the need for direct high-temperature wafer-to-wafer bonding or adhesive bonding, thus simplifying the overall process while maintaining hermeticity.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Ease of manufacture

If adhesive bonding is used for wafer-level packaging, then manufacturing cost is reduced, but reliability deteriorates due to adhesive outgassing

Engineering Contradiction:
Improvemanufacturing costVSAvoidhermeticity
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent changes the bonding mechanism from adhesive bonding (chemical bonding with outgassing) to glass frit bonding (viscous flow bonding). The glass frit material undergoes a rheological change at elevated temperature, transitioning from a solid to a viscous state that flows to form hermetic seals, then returns to solid upon cooling. This eliminates outgassing issues while maintaining hermeticity and is compatible with standard semiconductor packaging equipment.

Inventive Principle:
Principle #35Parameter changes

3Ease of manufacture

If LCP is used for packaging, then ease of manufacture is improved, but manufacturing precision deteriorates due to alignment requirements for cavity formation

Engineering Contradiction:
Improveease of manufactureVSAvoidalignment precision
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The patent segments the packaging process into distinct steps: first forming the package substrate with glass frit bonding, then separately forming cavities using laser drilling or etching. This segmentation allows each step to be optimized independently - the bonding step uses glass frit's self-aligning flow properties, while the cavity formation step uses precise laser or chemical methods, eliminating the need for complex alignment between these operations.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The glass frit layer serves as an intermediary that compensates for dimensional variations and misalignments between the semiconductor wafer and the package substrate. Its viscous flow特性 allows it to conform to surface irregularities and fill gaps, providing mechanical compliance and stress relief that accommodates thermal expansion differences and manufacturing tolerances.

Inventive Principle:
Principle #24Intermediary (Mediator)

4Ease of manufacture

If larger cavities are used in LCP packaging, then ease of manufacture is improved, but reliability worsens due to increased mechanical failure risk and compromised environmental protection

Engineering Contradiction:
Improvecavity formation easeVSAvoidmechanical strength
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent employs glass frit material that, when heated to its softening point, becomes a viscous liquid that flows into and fills all cavity spaces, including small and complex geometries. This porous-filling mechanism ensures complete hermetic sealing of the cavity walls without requiring the cavity itself to be large or simple in shape. The glass frit conformally coats all surfaces, providing uniform protection regardless of cavity size or complexity.

Inventive Principle:
Principle #31Porous materials

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach simplifies the packaging process, reduces stress on fragile structures, and enhances protection and performance by using a porous aerogel with high air content, providing effective environmental sealing and reduced parasitic capacitance.

Implementation Method 1

depositing a porous material in the device exposing openings over the devices

Methodology Applied
Scientific EffectPorous material deposition: Porosity

Implementation Method 2

forming device exposing openings and electrical contact exposing opening in a dielectric layer

Methodology Applied
Scientific EffectLithographic processing: Photography

Data Source

PatentUS8653673B2Method for packaging semiconductors at a wafer level
Publication Date: 2014.02.18 RAYTHEON CO
  • US8653673B2 patent drawing
  • US8653673B2 patent drawing
  • US8653673B2 patent drawing

AI summary

A package and method for packaging a semiconductor device formed in a surface portion of a semiconductor wafer. The package includes: a dielectric layer disposed on the surface portion of the semiconductor wafer having a device exposing opening to expose one of the devices and an electrical contacts pad opening to expose an electrical contact pad; and a porous material in the device exposing opening over said one of the devices.