Wafer Level Packaging Circuit Layer Fabrication and Yield Detection
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Solution Overview
Problem
Conventional wafer-level packaging methods face challenges in positioning accuracy due to the flexibility of thermal release tapes and high fabrication costs resulting from discarding good semiconductor components when low-quality circuit structures are detected after encapsulant formation.
Innovation Solution
A fabrication method involving the formation of a circuit layer on a carrier with dielectric layers and conductive bumps before removing the carrier, allowing for accurate positioning and quality detection of the circuit layer, thereby avoiding position errors and discarding good semiconductor components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If thermal release tape is used to carry semiconductor components, then ease of operation is improved, but positioning accuracy deteriorates due to CTE and lateral forces during molding
Solution Approach 1:
The patent extracts the circuit structure formation process from the semiconductor component mounting process. The circuit structure is formed directly on the carrier before mounting components, separating the circuit fabrication from the component assembly. This eliminates the positioning errors caused by thermal release tape flexibility and CTE expansion during molding, as the circuit structure is already fixed on the rigid carrier.
2Device complexity
If encapsulant is formed before RDL process, then device complexity is reduced, but productivity deteriorates due to yield losses from discarding good components
Solution Approach 1:
The patent performs preliminary quality detection of the circuit structure on the carrier before mounting semiconductor components. This allows early identification of low-quality circuit structures, enabling selective discarding of only the defective carriers while preserving good semiconductor components for use on other carriers. This preliminary action prevents the waste of good components that would occur if encapsulation were performed before quality verification.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enhances positioning accuracy and reduces fabrication costs by preventing position errors caused by thermal expansion and allowing for early detection and discard of low-quality circuit layers, improving yield and cost efficiency.
Implementation Method 1
forming an encapsulant on the second dielectric layer for encapsulating the semiconductor component
Data Source
AI summary
A fabrication method of a wafer level semiconductor package includes: forming on a carrier a first dielectric layer having first openings exposing portions of the carrier; forming a circuit layer on the first dielectric layer, a portion of the circuit layer being formed in the first openings; forming on the first dielectric layer and the circuit layer a second dielectric layer having second openings exposing portions of the circuit layer; forming conductive bumps in the second openings; mounting a semiconductor component on the conductive bumps; forming an encapsulant for encapsulating the semiconductor component; and removing the carrier to expose the circuit layer. By detecting the yield rate of the circuit layer before mounting the semiconductor component, the invention avoids discarding good semiconductor components together with packages as occurs in the prior art, thereby saving the fabrication cost and improving the product yield.