Wafer-Level Packaging with Integrated Thermal Heat Spreaders
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Solution Overview
Problem
Existing wafer-level packaging technologies for integrated circuits face challenges such as high RF and DC losses, increased cost, and package volume due to wire bonding and electroplated interconnects, as well as issues with heat spreader fabrication in compact packages, which require additional processing steps and can result in voids.
Innovation Solution
A method for wafer-level packaging that incorporates integrated thermal heat spreaders, hermetically-sealed cavities, and low-loss through-wafer interconnects, using silicon micromachining and electroplating technologies to form plated metal rings, seal rings, and heat spreaders, with thermocompression bonding and electroforming to achieve efficient thermal management and reduced interconnect losses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If wire bonds or electroplated interconnects are used to connect microelectronic chips to packaging, then electrical interconnection is achieved, but direct current (DC) and radio frequency (RF) losses increase
Solution Approach 1:
The patent merges the interconnection function with the package substrate by forming conductive interconnect structures directly within the package substrate that electrically connect the chip to external contacts, eliminating the need for separate wire bonds or electroplated interconnects. This integration reduces the number of interconnection components and minimizes energy losses.
Solution Approach 2:
The patent extracts the interconnection function from traditional wire bonding or electroplating processes and embeds it directly into the package substrate structure. By forming conductive paths within the substrate itself, the design removes the need for additional interconnection layers and reduces parasitic losses.
2Reliability
If additional processing steps for adding benzocyclobutene (BCB) layers are performed for packaging compatibility, then packaging integration is improved, but high-frequency losses increase due to increased parasitic capacitances
Solution Approach 1:
The patent applies local quality by using low-dielectric-constant materials specifically in regions where parasitic capacitance would affect RF performance. By selectively placing materials with optimized dielectric properties near high-frequency signal paths, the design minimizes parasitic capacitances while maintaining packaging compatibility without requiring additional BCB processing steps.
3Manufacturing precision
If sidewall electroplating followed by polishing is used for heat spreader fabrication, then heat spreaders can be formed, but voids appear inside the heat spreaders when fabricating very compact packages
Solution Approach 1:
The patent inverts the traditional heat spreader fabrication approach by using bottom-up electroplating instead of sidewall electroplating. By initiating plating from the substrate surface and building the heat spreader structure upward, the process eliminates void formation that occurs with sidewall plating in compact packages, while still achieving the required thermal management performance.
4Temperature
If the lateral dimensions of heat spreaders are incrementally larger than the lateral dimensions of the chips to be embedded, then thermal management coverage is improved, but voids appear inside the heat spreaders
Solution Approach 1:
The patent applies preliminary action by pre-forming the heat spreader structure with the correct lateral dimensions before chip embedding. By establishing the heat spreader's final geometry in advance through bottom-up electroplating, the design ensures adequate thermal coverage without creating voids, as the plating process naturally conforms to the desired dimensions without requiring incremental buildup.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution results in reduced RF and DC losses, lower manufacturing costs, and improved thermal management, with integrated heat spreaders enhancing chip performance by up to 40% and providing void-free heat spreaders, while maintaining hermetic seals and minimizing parasitic capacitive coupling.
Implementation Method 1
bonding the plated metal ring on the respective die to the respective plated seal ring
Implementation Method 2
electroforming a respective heat spreader in each cavity of the body wafer
Implementation Method 3
integrated thermal heat spreaders... providing void-free heat spreaders, while maintaining hermetic seals
Data Source
AI summary
A method for wafer level packaging includes forming one or more die, forming a plated metal ring (PMR) on each die, forming a cover wafer (CW), the CW having one or more plated seal rings, forming a body wafer (BW), the BW having cavities and a metal layer on a first side of the BW, aligning a respective die to the CW so that a PMR on the respective die is aligned to a respective plated seal ring (PSR) on the CW, bonding the PMR on the respective die to the respective PSR, aligning the BW to the CW so that a respective cavity of the BW surrounds each respective die bonded to the CW and so that the metal layer on the BW is aligned with at least one PSR on the CW, and bonding the metal layer on the first side of the BW to the PSR on the CW. Each PMR has a first height and each PSR has a second height.