Wafer-Level Packaging for LDMOS Transistors with Air-Gap Bond Wires
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Solution Overview
Problem
Conventional semiconductor packaging methods, especially for LDMOS power transistors, are costly due to individual packaging of each IC, and they often leave bond wires exposed to air, which can lead to parasitic coupling and thermal inefficiencies.
Innovation Solution
A wafer-level packaging method where passive components are fabricated on a wafer with recesses lined with conductive material, integrated circuits are placed inside these recesses, bonded with bond wires, and covered by a cap, allowing for simultaneous packaging of multiple ICs with optimized bond wire lengths for reduced parasitic coupling and improved thermal management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If individual packaging is used for each IC, then protection from environmental conditions is achieved, but packaging cost increases significantly
Solution Approach 1:
Multiple individual IC packages are merged into a single package module. Multiple IC chips are mounted on a common substrate and enclosed together in one package housing with a single lid, replacing the conventional approach of individually packaging each IC. This merging reduces the number of lids, seals, and packaging materials required, thereby significantly lowering packaging cost while maintaining environmental protection for each IC through internal spacing and the common sealed environment.
2Object-generated harmful factors
If bond wires are surrounded by air, then parasitic coupling is reduced, but thermal management efficiency deteriorates
Solution Approach 1:
Different regions of the package are assigned different materials with different properties. Bond wires are surrounded by air in the upper region near the IC chips to minimize parasitic coupling and maintain high Q levels. The substrate and lower region use materials with high thermal conductivity to provide efficient thermal pathways from the IC chips to the heat sink. This local differentiation of material properties simultaneously achieves both low parasitic coupling and effective thermal management.
3Reliability
If ceramic lid is used to seal the package, then environmental protection is improved, but manufacturing complexity and cost increase
Solution Approach 1:
The lid serves multiple functions simultaneously: it provides environmental sealing for all IC chips in the package, acts as a heat dissipation component with integrated heat sinks, and includes mounting structures for securing ICs and passive components. The substrate also serves dual purposes as both the mounting platform for ICs and the thermal conduction pathway to heat sinks. This multi-functionality reduces the number of separate components needed, simplifying the overall package structure while maintaining robust environmental protection.
Data Source
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AI summary
In an embodiment, a semiconductor device includes a semiconductor substrate. The semiconductor substrate has a first cavity disposed through it, and conductive material covers at least the bottom portion of the first cavity. An integrated circuit is disposed on the top surface of the conductive material. The device further includes a cap disposed on the top surface of the substrate, such that a cavity disposed on a surface of the cap overlies the first cavity in the substrate.