Wafer Level Packaging Using Lead-Frame Matrix
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Solution Overview
Problem
Current integrated circuit packaging methods for power regulation, such as multi-chip modules, stacked circuits, and monolithic circuits, are either expensive, wasteful of space, or degrade the performance of power transistors due to additional processing steps required for the controller chip.
Innovation Solution
A compact and cost-effective packaging solution using a lead-frame matrix with a controller die soldered onto a power transistor die, where the lead-frame matrix is fabricated with a specific pattern to accommodate differential expansion and allows for wafer-level processing, enabling efficient electrical connections and reducing unnecessary processing steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple circuits are packaged together side by side on a substrate as a multi-chip module, then multiple circuit functions are integrated in a single package, but the cost increases and printed circuit board area is wasted
Solution Approach 1:
The patent transitions from planar multi-chip module packaging to three-dimensional stacked packaging, where the controller die is positioned above the power transistor die vertically. This dimensional change enables multiple circuit functions to be integrated in a single package without increasing the printed circuit board footprint, while also reducing costs by eliminating the need for separate substrate interconnections.
2Adaptability or versatility
If two integrated circuits are stacked, then electrical connections are established, but the cost increases due to complex interconnections through the bottom chip
Solution Approach 1:
The patent segments the stacked package into two functional layers: the bottom layer contains the power transistor die with its substrate serving as the circuit board, and the top layer contains the controller die. This segmentation eliminates the need for complex through-chip interconnections, as the controller die connects to power transistor terminals directly on the substrate surface, significantly reducing manufacturing cost and complexity.
3Stability of the object's composition
If power transistors and controller are fabricated as a single monolithic circuit, then a truly monolithic device is achieved, but the cost increases substantially due to requiring full controller processing for all devices
Solution Approach 1:
The patent applies local quality by fabricating the power transistor die and controller die separately using their respective optimized processes, then packaging them together in a stacked configuration. This allows each die to be manufactured with the appropriate level of processing complexity for its function, avoiding the wasteful application of full controller-grade processing to simple power transistor structures, thereby significantly reducing cost while maintaining monolithic-like integration benefits.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a low-cost, high-performance packaging solution that maintains the integrity of both the controller and power transistors, reducing the overall cost and improving the performance of the packaged device.
Implementation Method 1
the lead-frame matrix is fabricated with a specific pattern to accommodate differential expansion
Implementation Method 2
a controller die soldered onto a power transistor die
Data Source
AI summary
Wafer level packaging using a lead-frame. When used to package two or more chips, a final product having QFN package-like finish. The final product will also have a performance rivaling or exceeding that of a corresponding monolithic chip because of the very close connection of the two or more chips and the ability to tailor the fabrication processing of each chip to only that required for the devices on that chip. The wafer level packaging can also be used to package monolithic chips, as well as chips having active devices on one chip and passive devices on a second chip. Various exemplary embodiments are disclosed.