Wafer-Level Packaging Module for Antenna Shielding and Thermal Management
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Solution Overview
Problem
Current wafer-level packaging technologies, such as eWLB and InFO, fail to adequately optimize antenna efficiency, shield electromagnetic interference, dissipate heat effectively, and reduce production costs, limiting the performance and applicability of miniaturized wireless systems operating at higher frequencies.
Innovation Solution
A wafer-level packaging module comprising an antenna board with a shielding element and a chip board with a rewiring layer and shielding layer, connected via electrically conductive elements, allowing for optimized integration and shielding of components, heat dissipation, and reduced production costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If antennas and chips are integrated on the same substrate in conventional wafer-level packaging, then miniaturization is achieved, but electromagnetic compatibility problems occur due to antenna stray fields interfering with chip functionality
Solution Approach 1:
The patent divides the integrated system into two separate boards: an antenna board for housing antenna elements and a chip board for mounting chips and passive components. This segmentation physically separates the antenna stray fields from the sensitive chip components, eliminating electromagnetic compatibility problems while maintaining the miniaturized form factor through close proximity integration of the two boards.
Solution Approach 2:
The patent introduces a shielding layer as an intermediary component between the antenna elements and the chips. This shielding layer acts as a mediator that blocks or redirects electromagnetic fields, preventing direct interference between antennas and chips while allowing both components to remain integrated in a compact package structure.
2Length of stationary object
If antenna elements are integrated on the same substrate as chips, then short links are achieved, but antenna efficiency is compromised due to limited design freedom
Solution Approach 1:
By separating antennas and chips onto different boards, the patent allows each board to be independently optimized. The antenna board can be designed with optimal antenna element placement, grounding, and matching structures for maximum efficiency, while the chip board can be optimized for short signal paths through advanced rewiring layers. The two boards are then connected through controlled impedance interfaces.
Solution Approach 2:
The patent transitions from planar integration on a single substrate to three-dimensional stacked integration with multiple layers. The antenna board and chip board are stacked vertically and connected through via structures and rewiring layers, enabling both long antenna elements for efficient radiation and short horizontal signal paths for high-speed data transmission.
3Power
If power amplifiers are integrated to increase system performance, then higher power output is achieved, but heat dissipation becomes a critical reliability issue
Solution Approach 1:
The patent separates high-power components (power amplifiers) from sensitive components (chips and passive components) onto different boards. This segmentation allows the antenna board to serve as a heat sink and radiation path for power amplifier heat, while the chip board maintains lower temperatures for sensitive electronics. Thermal management is further enhanced through the shielding layer which can be thermally conductive.
Solution Approach 2:
The shielding layer serves as a thermal intermediary between the antenna board and chip board. It can be designed with thermal conductivity to conduct heat away from chips while maintaining electromagnetic shielding functionality. This mediator enables effective heat dissipation paths without compromising signal integrity or electromagnetic compatibility.
4Device complexity
If conventional eWLB or InFO packaging is used, then integration is achieved, but production flexibility and cost reduction are limited
Solution Approach 1:
The patent uses two separate standard-sized boards (antenna board and chip board) that can be manufactured independently using conventional PCB and semiconductor fabrication processes. This segmentation allows each board to be produced in high volumes using optimized, cost-effective processes, then assembled together through standard interconnection techniques, improving production flexibility and reducing costs compared to monolithic integration.
Solution Approach 2:
The patent designs the module as a universal platform where the antenna board and chip board can be independently configured for different applications. The standardized board interfaces and connection methods allow the same basic structure to accommodate various antenna types, chip configurations, and passive component arrangements, enabling heterogeneous integration with high production flexibility across multiple product lines.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances system performance by optimizing individual component integration, reduces production costs, minimizes electromagnetic compatibility issues, and improves thermomechanical reliability and signal integrity, enabling more effective use of higher frequency bands in wireless systems.
Implementation Method 1
a shielding element introduced in an opposite shielding layer in the area of the at least one antenna element
Implementation Method 2
The two boards are connected to one another in the area of the chip by means of electrically conductive connecting elements
Data Source
AI summary
A wafer-level packaging based module includes an antenna board and a chip board. The antenna board includes at least one antenna layer with introduced antenna element and a shielding layer with introduced shielding element in the area of the at least one antenna element opposite to the antenna layer. The chip board includes a contacting layer, a rewiring layer opposite to the contacting layer and the shielding layer having at least one shielding element arranged on the rewiring layer. A chip layer having at least one chip is arranged between the contacting layer and the rewiring layer. Further, the chip layer includes at least one via connecting the contacting layer to the rewiring layer.