Wafer Level Packaging via Through Encapsulation Vias
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Solution Overview
Problem
The existing wafer level package manufacturing process is plagued by warpage defects and increased manufacturing time due to the use of molding materials, which degrades photomask process reliability and raises costs.
Innovation Solution
A method involving the formation of a repassivation layer to encapsulate semiconductor chips, through encapsulation via (TEV) formation, and redistribution layers with conductive bumps, eliminating the need for a molding process and using a supporting frame like a silicon or glass wafer to prevent warpage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a molding process is used to reconstitute wafer chips into a wafer form, then the chips can be packaged at wafer level, but warpage defects occur and photomask process reliability degrades
Solution Approach 1:
The patent extracts and removes the molding process from the wafer level packaging sequence. Instead of forming chips into a wafer form using molding material, the method processes chips in their isolated state through repassivation, TEV formation, and redistribution layer deposition, thereby eliminating the warpage defects caused by molding material characteristics
Solution Approach 2:
The patent inverts the conventional sequence by processing chips individually or in groups before reconstituting them into a wafer form, rather than molding them into wafer form first. The steps are performed on isolated chips or small groups, then the processed chips are reconstituted into a wafer form for final dicing, reversing the traditional approach to avoid warpage
2Reliability
If a molding process is used to reconstitute wafer chips into a wafer form, then encapsulation is achieved, but the total manufacturing time increases and yield rate decreases
Solution Approach 1:
The patent extracts the time-consuming molding process from the manufacturing sequence and replaces it with direct repassivation and encapsulation steps performed on isolated chips or small groups of chips. This eliminates the lengthy molding and demolding operations while maintaining encapsulation quality through the repassivation layer and subsequent encapsulant application
Solution Approach 2:
The patent segments the wafer level packaging process into smaller, manageable units by processing chips in groups or individually rather than requiring all chips to be molded together as a single wafer form. This segmentation allows parallel processing and eliminates the need for a single lengthy molding cycle, reducing total manufacturing time
3Productivity
If a molding process is used to reconstitute wafer chips, then a wafer form is created, but manufacturing cost increases
Solution Approach 1:
The patent removes the expensive molding process from the manufacturing sequence and replaces it with more cost-effective direct encapsulation methods. By processing chips through repassivation and encapsulation in their isolated state or in small groups, the method eliminates molding material costs, mold frame costs, and the complex equipment requirements associated with molding
Solution Approach 2:
The patent employs simpler, less expensive encapsulation materials and methods compared to the durable molding materials and mold frames required in conventional processes. The repassivation layer and encapsulant can be applied using standard semiconductor fabrication techniques rather than requiring expensive molding equipment and materials
Data Source
AI summary
Provided is a method of manufacturing a wafer level package. The method includes forming a repassivation layer that encapsulates a plurality of semiconductor chips isolated from a wafer, forming a through encapsulation via (TEV) in the repassivation layer, forming a redistribution layer electrically connected to the TEV, and forming a bump ball on the redistribution layer.