Wafer-Level Packaging Thickness Reduction via Under-Bump Metal Layers
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Solution Overview
Problem
In semiconductor fabrication, the increasing functional demands of chips lead to higher packaging requirements, particularly in flip and stack packaging, where thinness is desired, but this can increase processing risks due to structural vulnerabilities.
Innovation Solution
A wafer-level packaging method involving forming an under-bump metal layer on a first chip, connecting a second chip to it, and creating a filling layer between them, with a solder ball on a connecting member that forms a height difference, allowing for flip packaging without damaging the chip structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If the packaging thickness is reduced to achieve thinner chip packaging, then the packaging thickness is improved, but the processing risks are increased
Solution Approach 1:
The method forms an under-bump metal layer on the first chip before connecting the second chip, and creates a filling layer between the chips. This preliminary preparation of metal layers and filling structures ensures that when flip packaging is performed, the chips have sufficient structural support and connection stability, thereby reducing processing risks while achieving thin packaging thickness
Solution Approach 2:
The under-bump metal layer and filling layer act as intermediary structures between the first and second chips. These intermediary layers provide mechanical support and stress distribution during the flip packaging process, preventing direct contact and potential damage between chip surfaces, thus reducing processing risks while maintaining thin overall thickness
2Length of stationary object
If flip packaging is performed to reduce packaging thickness, then the packaging thickness is improved, but the chip structure may be destroyed
Solution Approach 1:
The under-bump metal layer is formed on the functional surface of the first chip before the second chip is connected. This preliminary metal layer provides a robust bonding interface that can withstand the mechanical stresses of flip packaging, ensuring chip structure integrity while enabling thin packaging
Solution Approach 2:
The filling layer is formed between the first and second chips, creating a cushioning structure that absorbs and distributes mechanical stresses during flip packaging. This beforehand cushioning prevents direct impact forces from damaging the chip structures, maintaining strength while achieving reduced packaging thickness
Data Source
AI summary
The present disclosure discloses a fabrication method for wafer-level packaging, comprising: forming a first photoresist on a first chip and a plurality of first openings at the first photoresist to expose a functional surface of the first chip, forming an under-bump metal layer on the functional surface exposed through the plurality of first openings, and removing the first photoresist; connecting a functional solder bump of a second chip to the under-bump metal layer on the first chip; forming a filling layer between the first chip, and the second chip; and forming a connecting member on the first chip, wherein a solder ball is disposed at a top surface of the connecting member, and an apex of the solder ball is higher than a top surface of the second chip.