Wafer Level Packaging Vertical Vias for MEMS
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Solution Overview
Problem
Existing wafer level packaging techniques for MEMS devices face challenges such as long feed-through lines leading to high parasitic capacitances and interconnection resistances, rigidity issues in glass wafers, and thermal stress due to thermal expansion mismatch between substrates and metal fillings, which affect device reliability and performance.
Innovation Solution
The solution involves forming vertical vias on one side of the bonded wafer stack using anodic bonding, thermal compression bonding, or glass frit bonding, with a cap wafer bonded to a MEMS wafer, and partially filling the vias with metal to minimize thermal stress and parasitic capacitances, allowing for a well-defined cap gap and flexible operation of MEMS structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If lateral feed-through lines are used to provide electrical lead-outs, then the bonding process can be simplified, but the parasitic capacitances and interconnection resistances increase significantly
Solution Approach 1:
The patent transitions from lateral (2D) feed-through lines to vertical (3D) through-vias for electrical lead-outs. This dimensional change shortens the current path, reducing parasitic capacitance and resistance while maintaining bonding process simplicity. The vertical via structure allows direct connection through the bond interface rather than along the surface.
2Ease of manufacture
If glass wafer thickness is increased to provide substrate rigidity for via forming, then via formation becomes easier, but parasitic coupling capacitances increase and manufacturing cost rises
Solution Approach 1:
The patent optimizes glass wafer thickness to a specific range (50-200 micrometers) that balances mechanical rigidity for via formation with electrical performance. This parameter optimization allows sufficient stiffness for via processing while minimizing parasitic coupling capacitance between adjacent vias, avoiding both excessive thickness and insufficient rigidity.
3Reliability
If vias are completely filled with metal for feed-through paths, then electrical connectivity is improved, but thermal stress increases due to thermal expansion mismatch
Solution Approach 1:
The patent employs partial via filling where metal is deposited only to a portion of the via depth rather than complete filling. This partial action provides sufficient electrical connectivity for feed-through while reducing the volume of metal that causes thermal expansion mismatch stress, thereby lowering overall thermal stress in the structure.
Solution Approach 2:
The patent applies different material properties to different regions of the via structure. The via is partially filled with metal for electrical connectivity while leaving the upper portion empty or filled with dielectric material, creating local quality variations that reduce thermal stress concentration while maintaining electrical function.
4Ease of operation
If deep trenches are etched and filled with dielectric material for silicon cap via formation, then vertical feed-through paths are achieved, but process complexity and stress issues increase
Solution Approach 1:
The patent extracts the via formation process from the silicon cap wafer and performs it directly on the glass substrate wafer. This eliminates the need for complex deep trench etching, dielectric filling, and recess formation in silicon, significantly reducing process steps and associated stress issues while achieving the same vertical feed-through functionality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in minimized feed-through resistance and coupling capacitance, improved thermal stability, and enhanced reliability and performance of MEMS devices with reduced manufacturing costs and complexity, particularly suitable for large wafer formats.
Implementation Method 1
the glass wafer is bonded to a MEMS silicon wafer by anodic bonding to form a hermetic package
Implementation Method 2
forming vertical vias on one side of the bonded wafer stack using anodic bonding, thermal compression bonding, or glass frit bonding
Implementation Method 3
fill up the glass vias with metal(s) electro-plated studs
Data Source
AI summary
Wafer level packaging process for packaging MEMS or other devices. In some embodiments, a MEMS wafer with normal thickness is firstly bonded to a cap wafer of normal thickness, followed by a thinning on the backside of the MEMS wafer. After this, the bonded wafer stack and the capping of the hermetically packaged MEMS devices are still rigid enough to do further processing. On this basis, through vias on the thinned substrate can be easily formed and stopped on the regions to be led out (e.g., metal pads/electrodes, highly doped silicon, etc.). Vias can be partially filled as this is the final surface of process. Even thick metal coated/patterned vias have much more space to relax possible thermal stress, as long as the vias are not completely filled with hard metal(s). Various embodiments are disclosed.