Wafer-Level Passivation Voids for IC Package Alignment
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Solution Overview
Problem
The existing integrated circuit (IC) package manufacturing process is costly and unreliable due to the complex operations involved in applying protective layers, forming openings, and aligning vias in the passivation and dielectric layers, which leads to inefficiencies and misalignment.
Innovation Solution
The process involves forming a wafer with an unpatterned passivation layer, laminating a dielectric layer, selectively removing dielectric material to form voids that align with the passivation layer, and using a wet etch process to expose metal conductors, followed by depositing barrier and seed layers, and a redistribution layer to ensure accurate alignment and reliable connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If openings are formed in the passivation layer at the foundry using resist material as a mask, then metal contacts can be exposed, but the process becomes costly due to resist material removal and oxidation prevention requirements
Solution Approach 1:
The patent applies preliminary action by forming the openings in the passivation layer at the wafer level during initial processing, before the die is separated and packaged. This allows the openings to be pre-formed with proper alignment features, eliminating the need for costly resist material and subsequent alignment operations at the packaging stage. The metal contacts are exposed in advance, and the wafer can be stored and transported without oxidation issues since the openings are already formed and sealed.
Solution Approach 2:
The patent introduces an intermediary alignment feature layer between the passivation layer openings and the dielectric layer vias. This intermediary layer provides reference marks that enable precise alignment during subsequent processing steps, eliminating the need for expensive alignment equipment and reducing misalignment errors. The intermediary features serve as a bridge that transfers alignment information from the wafer-level openings to the package-level vias.
2Manufacturing precision
If openings in the passivation layer are formed prior to disposition of the dielectric layer, then alignment between vias and openings becomes difficult, but forming openings later increases process complexity
Solution Approach 1:
The patent forms the passivation layer openings at the wafer level before applying the dielectric layer, establishing the opening positions and alignment features in advance. This preliminary action creates a stable reference framework that guides subsequent via formation, ensuring precise alignment without requiring complex real-time alignment systems during packaging operations.
Solution Approach 2:
The patent introduces intermediary alignment features that are formed between the passivation layer and the dielectric layer. These intermediary features serve as alignment references that simplify the via formation process, allowing standard packaging equipment to achieve precise alignment without requiring complex coordination between multiple processing steps.
3Reliability
If a complex series of operations is used to produce the IC package, then protective layers can be applied and openings formed, but the manufacturing process becomes costly and time-consuming
Solution Approach 1:
The patent consolidates multiple operations into preliminary wafer-level processing, including protective layer application, opening formation, and alignment feature creation. By completing these operations before die separation and packaging, the patent eliminates the need for repeating these steps during package assembly, significantly improving manufacturing efficiency and reducing cycle time while maintaining connection reliability.
Solution Approach 2:
The patent merges multiple discrete operations into integrated wafer-level processing steps. The protective layer application, opening formation, and alignment feature creation are combined into a coordinated sequence performed on the entire wafer before dicing, rather than performing separate operations on individual dies during packaging. This merging reduces process complexity and improves throughput.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces manufacturing costs and enhances the reliability and consistency of IC package connections by ensuring precise alignment and prevention of oxidation, resulting in a more efficient and reliable IC package assembly.
Implementation Method 1
a wet etch process to expose metal conductors
Data Source
AI summary
Embodiments of the present disclosure are directed towards a method of assembling an integrated circuit package. In embodiments the method may include providing a wafer having an unpatterned passivation layer to prevent corrosion of metal conductors embedded in the wafer. The method may further include laminating a dielectric material on the passivation layer to form a dielectric layer and selectively removing dielectric material to form voids in the dielectric layer. These voids may reveal portions of the passivation layer disposed over the metal conductors. The method may then involve removing the portions of the passivation layer to reveal the metal conductors. Other embodiments may be described and/or claimed.