Wafer-Level Passive Array Packaging for Compact Modules
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Solution Overview
Problem
Current microelectronic packaging technologies face challenges in integrating passive components within smaller spaces, leading to increased module size and reduced vertical packing density, especially when combined with taller components.
Innovation Solution
The implementation of wafer-level passive array (WLPA) packaging techniques, where passive components are vertically integrated underneath the die within the package, bonded to both the die and circuit board, utilizing a redistribution layer (RDL) and different solder materials for alignment and mounting, allowing for reduced module area and increased vertical packing density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If passive components are mounted adjacent to the die on the circuit board, then supplemental features such as filtering and power supply are provided, but the module footprint increases
Solution Approach 1:
The passive components are positioned directly underneath the die in a nested configuration, with the die serving as the outer layer and passive components nested within its shadow area. This nesting approach allows passive components to occupy space that would otherwise be unused, providing filtering and power supply functions while maintaining a compact module footprint.
Solution Approach 2:
The invention transitions from a two-dimensional planar arrangement where passive components are mounted adjacent to the die on the circuit board, to a three-dimensional vertical arrangement where passive components are positioned underneath the die. This dimensional change充分利用 vertical space, reducing the horizontal footprint while maintaining functional completeness.
2Reliability
If taller passive components are integrated into the module, then additional functionality is provided, but vertical packing density is reduced
Solution Approach 1:
Cavities are pre-formed in the circuit board at strategic locations before component assembly. These cavities are designed to accommodate taller passive components, allowing them to be integrated into the module without compromising vertical packing density. The preliminary preparation of cavities ensures that vertical space is efficiently utilized while providing necessary functional capabilities.
3Manufacturing precision
If passive components are bonded with high reflow temperature solder material, then alignment precision is improved, but the mounting process complexity increases
Solution Approach 1:
The invention employs a dual solder material strategy with different reflow temperature parameters. High reflow temperature solder material is used for bonding passive components to the die to ensure alignment precision, while low reflow temperature solder material is used for bonding the package to the circuit board to simplify the mounting process. This parameter differentiation allows each bonding step to be optimized independently, achieving high precision without excessive overall process complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces module area, increases vertical packing density, and enhances electrical connectivity by routing signals through passive components, providing additional functionality and reducing circuit board routing length for sensitive signals.
Implementation Method 1
The plurality of passive components is bonded to the die with a first solder material and bonded to the circuit board with a second solder material. The first solder material may be characterized by a higher reflow temperature than the second solder material.
Data Source
AI summary
Wafer level passive array packages and modules are described. In an embodiment, a module includes a circuit board, and a package mounted on the circuit board in which the package includes a plurality of passive components bonded to a bottom side of the die and a plurality of landing pads of the circuit board.