Wafer Level Semiconductor Package Power Distribution
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Solution Overview
Problem
Semiconductor chips with high integration density and fast data processing speed face heat generation issues, leading to performance degradation, and struggle to provide sufficient power due to limited area and internal wiring constraints, especially at the edge portions.
Innovation Solution
A wafer level semiconductor package design that includes a bonding pad group, internal circuit patterns, additional power pads, insulation layers, and a redistribution layer to efficiently connect and distribute power, allowing for independent power provision to the semiconductor chip, including the use of a protective layer and capping layer with solder balls for enhanced connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If a larger number of power supplying pads are formed in the semiconductor chip, then sufficient power can be provided to the chip, but the chip area increases
Solution Approach 1:
The patent extends power supply from the traditional bonding pad area to the entire chip surface by forming additional power pads and internal circuit patterns across the chip area. This multi-dimensional power distribution network allows power to be supplied from multiple locations simultaneously, increasing power capability without requiring a proportional increase in bonding pad area.
Solution Approach 2:
The power supply function is segmented into multiple independent power pads (bonding pad group and additional power pads) distributed across different chip regions. Each power pad can be independently connected to power supply terminals, allowing the total power capability to be the sum of individual pad contributions without requiring any single pad to be excessively large.
2Adaptability or versatility
If internal wiring is used to provide power to the edge portion of the semiconductor chip, then power can be distributed to specific portions, but sufficient power cannot be provided to the edge portion due to wiring resistance
Solution Approach 1:
The patent creates locally optimized power supply regions by placing additional power pads at specific chip locations (including edge portions) and providing dedicated internal circuit patterns to each region. Each local region has its own power entry point and optimized wiring path, minimizing the distance current must travel through high-resistance internal wiring and reducing overall wiring resistance effects.
Data Source
AI summary
A wafer level semiconductor package includes a semiconductor chip having a circuit part. A bonding pad group is disposed in the semiconductor chip and included in the bonding pad group is a power pad that is electrically connected to the circuit part. An internal circuit pattern is disposed at a side of the bonding pad group. An additional power pad is disposed at a side of the bonding pad group, and the additional power pad is electrically connected to the circuit part. An insulation layer pattern is disposed over the semiconductor chip, and the insulation layer includes openings that expose the power pad, the internal circuit pattern, and the additional power pad. A redistribution is disposed over the insulation layer pattern, and the redistribution is electrically connected to at least two of the power pad, the internal circuit pattern, and the additional power pad.