Wafer-Level Quartz Resonator Packaging for Two-Sided Testing

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Solution Overview

Problem

Conventional quartz crystal resonator structures have low packaging efficiency and reliability due to individual assembly processes, which hinder miniaturization and increase manufacturing costs.

Innovation Solution

A wafer-level packaged resonator design with integrated electrodes and solder pads on both sides of a quartz blank, allowing for testing on both sides without flipping and eliminating external connections, and utilizing staggered through-holes for enhanced interconnection strength and reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If conventional individual assembly process is used for quartz crystal resonator packaging, then each resonator can be assembled with proper connections, but packaging efficiency is low and manufacturing cost increases

Engineering Contradiction:
Improvepackaging efficiencyVSAvoidmanufacturing cost
Core Design Contradiction:
ProductivityVSEase of manufacture

Solution Approach 1:

The patent merges multiple individual resonator assembly operations into a single wafer-level processing step. Multiple resonators are packaged simultaneously on a wafer substrate, with electrodes and solder pads integrated directly into the packaging structure, eliminating the need for separate assembly operations for each resonator and achieving high-volume production efficiency

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The wafer substrate serves multiple functions simultaneously: it acts as the packaging carrier, provides electrical connections through integrated solder pads, supports electrode mounting, and enables batch processing of multiple resonators. This multi-functionality reduces the number of separate components and assembly steps required

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Productivity

If external connecting parts are installed on single blanks, then electrical connections can be established, but packaging efficiency decreases due to additional installation steps

Engineering Contradiction:
Improvepackaging efficiencyVSAvoidstructure complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent combines the external connecting parts (solder pads and electrodes) directly into the packaging structure during wafer-level fabrication. The solder pads are formed as integral parts of the wafer substrate, and electrodes are mounted directly onto the wafer, eliminating the need for separate installation steps and reducing overall structural complexity

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The solder pads and electrode mounting positions are prepared in advance during wafer fabrication before individual resonator separation. This preliminary preparation of connection structures eliminates the need for installing external connecting parts after resonator assembly, streamlining the packaging process

Inventive Principle:
Principle #10Preliminary action

3Productivity

If back solder pads are identified during final inspection, then connection quality can be verified, but test efficiency is reduced due to additional inspection steps

Engineering Contradiction:
Improvetest efficiencyVSAvoidinspection complexity
Core Design Contradiction:
ProductivityVSDifficulty of detecting and measuring

Solution Approach 1:

Instead of placing solder pads only on the back side of resonators requiring inspection from that side, the patent positions solder pads on the front side of the wafer, making them accessible for inspection from the front. This inversion of the traditional back-side-only solder pad arrangement allows for more efficient testing without requiring resonator flipping or complex back-side inspection equipment

Inventive Principle:
Principle #13The other way round (Inversion)

4Ease of manufacture

If wafer-level packaging is implemented without external connections, then manufacturing cost reduces and integration improves, but interconnection strength must be enhanced to maintain reliability

Engineering Contradiction:
Improvemanufacturing costVSAvoidinterconnection strength
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent implements a nested structure where multiple resonators are integrated within a single wafer packaging unit. The resonators, electrodes, and solder pads are all nested within the wafer substrate structure, creating a compact integrated assembly that reduces manufacturing complexity and cost while maintaining connection integrity through the nested arrangement

Inventive Principle:
Principle #7Nested doll (Nesting)

Solution Approach 2:

The patent merges the interconnection function directly into the wafer substrate structure, eliminating separate external connection components. The solder pads and electrode mounts are formed as integral parts of the wafer, creating strong built-in connections that reduce reliability concerns associated with separate external connectors while lowering manufacturing cost

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Improves testing efficiency, reduces manufacturing costs, and enhances product integration and reliability by enabling wafer-level packaging without external connections and external test positions.

Implementation Method 1

A quartz blank, both sides of which are provided with a first electrode and a second electrode respectively

Methodology Applied
Scientific EffectPiezoelectric effect: Piezoelectric Effect

Data Source

PatentUS20250293667A1Wafer-level packaged resonator and preparation method thereof, and electronic equipment
Publication Date: 2025.09.18 TKD SCIENCE & TECHNOLOGY CO LTD
  • US20250293667A1 patent drawing
  • US20250293667A1 patent drawing
  • US20250293667A1 patent drawing

AI summary

The present application provided a wafer-level packaged resonator and a preparation method therefor, as well as an electronic equipment, relating to the technical field of resonators. The electronic equipment includes a wafer-level packaged resonator. The wafer-level packaged resonator includes a quartz blank, both sides of which are provided with a first electrode and a second electrode respectively; a first packaging substrate, packaged on one side of the quartz blank provided with the first electrode, and a first solder pad and a second solder pad are provided with intervals on the side of the first packaging substrate away from the quartz blank; a second packaging substrate, packaged on the other side of the quartz blank, and a third solder pad and a fourth solder pad are provided on the side of the second packaging substrate away from the quartz blank.