Wafer-Level Semiconductor Package Interconnect Density
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Solution Overview
Problem
Conventional semiconductor packages with interposers have low input/output density and increased size, affecting electrical and thermal performance, while manufacturers and consumers seek smaller, more functional devices.
Innovation Solution
A method involving placing chips on a metallic layer, depositing mold material, selectively exposing the metallic layer, and covering it with conductive material to create singulated semiconductor packages entirely at the wafer level, enhancing interconnect density and reducing package size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an interposer is used in the semiconductor package, then the chip can be coupled to the outside world, but the package size increases and input/output density decreases
Solution Approach 1:
The patent removes the interposer component from the semiconductor package structure entirely. Instead of using a separate interposer substrate to couple chips to the outside world, the invention directly connects chips to the package substrate through wire bonds, eliminating the intermediate interposer layer and thereby reducing package size while maintaining connectivity functionality.
Solution Approach 2:
The patent merges the functions of the interposer and the package substrate into a single integrated structure. The package substrate directly provides both the mechanical support and the electrical interconnection functions that were previously separated between the interposer and the substrate, thereby reducing the overall package footprint while maintaining all necessary connectivity functions.
2Reliability
If an interposer is used in the semiconductor package, then the chip can be coupled to the outside world, but the input/output density decreases
Solution Approach 1:
By removing the interposer layer, the patent eliminates the additional routing layer that would be required to connect chips through the interposer to the outside world. This direct connection approach reduces the number of interconnection layers needed, thereby increasing the effective input/output density by providing more available routing resources within the reduced package structure.
Solution Approach 2:
The patent transitions from a multi-layer vertical interconnection approach (through the interposer) to a more direct, optimized routing topology. By reorganizing the interconnection architecture to eliminate the interposer, the design achieves higher I/O density by optimizing the spatial arrangement of connection points and routing paths within the available package footprint.
3Reliability
If an interposer is used in the semiconductor package, then the chip can be coupled to the outside world, but the electrical and thermal performance is adversely affected
Solution Approach 1:
The patent removes the interposer component that was causing electrical and thermal performance degradation. By eliminating this intermediate layer, the design achieves shorter current paths with lower resistance and improved thermal conduction, thereby reducing energy loss while maintaining reliable chip connectivity to the outside world.
Solution Approach 2:
The patent segments the interconnection function into direct wire bonds from the chip to the package substrate, eliminating the need for through-interposer vias and complex multi-layer routing. This segmented approach reduces the total interconnection length and number of interfaces, thereby improving electrical performance by reducing resistive losses and enhancing thermal performance by providing more direct heat dissipation paths.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the fabrication of smaller, more functional semiconductor packages with improved electrical and thermal performance by increasing input/output density and reducing package size, suitable for various electronic devices, including power devices.
Implementation Method 1
a common metallic layer configured to underlie the chips and provide separate interconnects to separate contacts for each of the chips
Implementation Method 2
a polymer dielectric disposed between chips placed on the common metallic layer
Implementation Method 3
conductive material is deposited onto the selectively exposed portion of the metallic layer
Data Source
AI summary
One embodiment provides a method of manufacturing semiconductor devices. For example, a sawn and expanded wafer is utilized having dielectrical material deposited between the diced and deposited chips. The method includes placing at least two chips on a metallic layer, depositing mold material on the metallic layer and between the chips, and selectively removing a portion of the mold material from the metallic layer to selectively expose a portion of the metallic layer. The method additionally includes covering the selectively exposed portion of the metallic layer with a conductive material, and singulating the at least two chips.