Wafer-Level Semiconductor Package Fabrication for Thin Interposers

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Solution Overview

Problem

Conventional methods for fabricating semiconductor packages with through electrodes on interposers face challenges in handling efficiency due to the thinness of semiconductor interposers, leading to potential damage and reduced yield, as well as difficulties in forming through electrodes and filling materials in the interposers.

Innovation Solution

A method involving mounting semiconductor chips on a semiconductor wafer, forming a mold resin, and then dicing the wafer to create individual packages, with optional support members and grinding to achieve the desired thickness, allowing for improved handling and mechanical strength, and enabling the formation of rewiring layers on both surfaces.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Length of stationary object

If the semiconductor interposer is shaped to be thinner to minimize package size, then the package thickness is reduced, but the handling ability during packaging process deteriorates and work efficiency is lowered

Engineering Contradiction:
Improvepackage thicknessVSAvoidhandling ability
Core Design Contradiction:
Length of stationary objectVSEase of operation

Solution Approach 1:

The patent applies preliminary action by performing the resin molding process on the wafer before dicing it into individual packages. This sequence allows the resin to provide structural support during handling and processing, enabling the interposer to be thin while maintaining handling ability. The wafer-level processing also allows batch handling, improving work efficiency before the final thin-profile packages are created through dicing.

Inventive Principle:
Principle #10Preliminary action

2Length of stationary object

If the semiconductor interposer is shaped to be thinner, then the package size is minimized, but the ability to form through electrodes and fill material in the through holes deteriorates

Engineering Contradiction:
Improveinterposer thicknessVSAvoidthrough electrode formation
Core Design Contradiction:
Length of stationary objectVSEase of manufacture

Solution Approach 1:

The patent performs through electrode formation and material filling on the wafer-level interposer before dicing into individual packages. This preliminary action at the wafer level provides several advantages: the larger wafer structure offers better mechanical support during these complex manufacturing steps, batch processing improves efficiency, and the subsequent dicing creates thin-profile packages that maintain the formed through electrodes. This sequence resolves the contradiction by enabling through electrode formation in a thicker wafer structure while achieving thin final packages.

Inventive Principle:
Principle #10Preliminary action

3Ease of operation

If the semiconductor interposer is made thicker to improve handling ability, then work efficiency is improved, but the package thickness increases undesirably

Engineering Contradiction:
Improvehandling abilityVSAvoidpackage thickness
Core Design Contradiction:
Ease of operationVSLength of stationary object

Solution Approach 1:

The patent uses preliminary wafer-level resin molding to provide structural support and improve handling ability during processing. The resin-impregnated wafer can be handled efficiently in batch mode during dicing and subsequent processing steps. After these operations are complete, the wafer is diced into individual thin-profile packages. This approach allows the interposer to be thin in the final package while maintaining improved handling during manufacturing through the preliminary resin molding and batch processing approach.

Inventive Principle:
Principle #10Preliminary action

4Productivity

If wafer-level resin molding and dicing is used instead of handling thin interposers, then handling efficiency and work efficiency are improved, but the process complexity increases

Engineering Contradiction:
Improvework efficiencyVSAvoidprocess complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent merges multiple operations into wafer-level processing: resin molding is performed on the entire wafer at once rather than on individual interposers, and dicing is performed on the wafer as a single unit. This merging of operations at the wafer level improves productivity through batch processing and reduces the cumulative complexity that would result from repeating individual operations on each thin interposer separately. The process complexity is managed by consolidating steps that would otherwise require multiple handling cycles.

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances handling efficiency and mechanical strength during packaging, reduces damage to semiconductor chips, and facilitates the formation of through electrodes and external terminals, improving the overall yield and reliability of semiconductor packages.

Implementation Method 1

forming a mold resin over the semiconductor chips to cover the semiconductor chips entirely

Methodology Applied
Scientific EffectEncapsulation:

Implementation Method 2

a support member is adhered onto a second surface of the semiconductor wafer

Methodology Applied
Scientific EffectAdhesion: Adhesive

Implementation Method 3

a second surface of the semiconductor wafer, which is the opposite the first surface, is ground to shape the semiconductor wafer thinner

Methodology Applied
Scientific EffectAbrasion: Abrasion

Data Source

PatentUS7413925B2Method for fabricating semiconductor package
Publication Date: 2008.08.19 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US7413925B2 patent drawing
  • US7413925B2 patent drawing
  • US7413925B2 patent drawing

AI summary

According to this invention, a method for fabricating a semiconductor package, in which a plurality of semiconductor chips having a through electrode is layered on a semiconductor interposer, comprising: mounting and layering a plurality of semiconductor chips on a first surface of a semiconductor wafer, which is to be used for a semiconductor interposer; forming a mold resin over the semiconductor chips to cover the semiconductor chips entirely; and dicing the semiconductor wafer to form a plurality of individual semiconductor packages.