Wafer Level Semiconductor Package Fan-Out Interposer Design
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Solution Overview
Problem
The increasing complexity of semiconductor devices requires more contact pads, leading to greater process complexity and cost in forming and routing electrical connections, as traditional wafer level packaging is limited to fan-in configurations and struggles to accommodate the growing number of pads.
Innovation Solution
A semiconductor package design that includes a semiconductor die, an interposer element with conductive vias, and a package body with a lower redistribution layer, allowing for both two-dimensional and three-dimensional fan-out configurations, enabling electrical connections to be made outside the periphery of the semiconductor device, thereby reducing manufacturing complexity and cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the number of contact pads is increased to support increased functionality, then the electrical connectivity capability is improved, but the process complexity and manufacturing cost increase
Solution Approach 1:
The patent transitions from traditional two-dimensional pad arrangements confined to the die perimeter to three-dimensional fan-out configurations where pads extend beyond the die edges through an overhang structure. This dimensional change allows multiple pads to be formed from a single die surface, dramatically increasing connectivity capability without proportionally increasing process complexity
Solution Approach 2:
The patent divides the package structure into distinct functional zones: the die area, the overhang region extending beyond the die perimeter, and the mold compound encapsulation. This segmentation allows independent optimization of each region, with the overhang specifically dedicated to housing extended pads and interconnect structures, thereby managing complexity through structured division
2Quantity of substance
If contact pads are located outside the periphery of the semiconductor device, then the connectivity density is improved, but the manufacturing process complexity increases
Solution Approach 1:
The patent performs preliminary actions by forming the overhang structure and extending pads before final encapsulation with mold compound. The interconnect structures are pre-positioned in the overhang region, and the redistribution layers are formed in advance, allowing subsequent steps to simply complete the encapsulation and connection processes without complex real-time adjustments
Solution Approach 2:
The patent introduces an overhang structure as an intermediary element between the die and the external environment. This overhang acts as a buffer zone that houses extended pads and interconnect structures, mediating the transition from confined die-level connections to package-level connections, thereby simplifying the overall manufacturing process
3Adaptability or versatility
If more contact pads are accommodated on the semiconductor package, then the functionality is improved, but the manufacturing cost increases
Solution Approach 1:
The patent creates a universal overhang structure that can accommodate multiple different pad configurations and interconnect arrangements within the same basic framework. This multi-functional design allows the same manufacturing process to produce various package types with different connectivity requirements, reducing tooling costs and process reconfiguration expenses
Solution Approach 2:
The patent merges multiple functions into the overhang structure: it serves as both a mechanical extension of the die, a housing for extended pads, a support for interconnect structures, and a transition zone for signal routing. This consolidation of functions into a single structural element reduces the total number of discrete components and assembly steps, thereby lowering manufacturing cost
Data Source
AI summary
A semiconductor package includes at least one semiconductor die having an active surface, an interposer element having an upper surface and a lower surface, a package body, and a lower redistribution layer. The interposer element has at least one conductive via extending between the upper surface and the lower surface. The package body encapsulates portions of the semiconductor die and portions of the interposer element. The lower redistribution layer electrically connects the interposer element to the active surface of the semiconductor die.