Wafer-Level Stacked Si Package With Thin-Film Redistribution Layers
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Solution Overview
Problem
Existing semiconductor package technologies face challenges in achieving thinner form factors and higher wiring density due to the limitations of laminate substrates, leading to poor manufacturability and high costs.
Innovation Solution
The method involves building up redistribution layers using wafer-level processing and performing stacking and wire bonding of dies as a wafer-level process, utilizing thin film redistribution layers with precise dimensions to create a semiconductor device package that is thinner and denser than traditional laminate-based packages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If traditional laminate substrates are used for semiconductor packaging, then structural support and electrical connectivity are provided, but the package thickness cannot be reduced and wiring density is limited
Solution Approach 1:
The patent extracts the substrate function from the traditional laminate structure and implements it directly on the wafer carrier through deposited redistribution layers. This eliminates the need for a separate laminate substrate, reducing package thickness while maintaining electrical connectivity and support functions through thin-film deposition techniques
Solution Approach 2:
The patent transitions from planar wiring on a laminate substrate to three-dimensional stacked architecture with vertical interconnects through redistribution layers. This dimensional change enables higher wiring density by utilizing vertical space for signal routing between stacked dies, thereby reducing the horizontal footprint and overall package thickness
2Quantity of substance
If laminate substrates are used to provide electrical pathways, then connectivity is achieved, but wiring density increases are limited and costs increase
Solution Approach 1:
The patent merges the substrate and wiring functions into a single integrated structure where redistribution layers are directly formed on the wafer carrier. This consolidation eliminates the need for separate laminate substrate and its complex multi-layer wiring structure, achieving high wiring density through thin-film deposition while simplifying the manufacturing process and reducing costs
Solution Approach 2:
The patent changes the physical parameters of the wiring structure by using thin-film deposition to create redistribution layers with controlled thickness and pattern density. This enables higher wiring density through precise parameter control of layer thickness, material composition, and pattern geometry, achieving compact routing without increasing manufacturing complexity
3Volume of moving object
If wafer-level processing is used to build redistribution layers, then package thickness is reduced and wiring density increases, but process complexity increases
Solution Approach 1:
The patent performs wafer-level processing to build redistribution layers and stack dies before final packaging. This preliminary action allows all complex thin-film deposition, patterning, and stacking operations to be completed while the wafer is still on the carrier, enabling subsequent singulation to produce multiple finished packages simultaneously. This approach reduces individual package complexity while maintaining high wiring density and thin profile
Data Source
AI summary
The disclosed method may include using a wafer-level process to build up a plurality of redistribution layers. The method may additionally include wafer-level mounting a plurality of flip chip die atop the plurality of redistribution layers. The method may also include wafer-level wire bonding the plurality of flip chip die to the plurality of redistribution layers. Various other methods, systems, and computer-readable media are also disclosed.