Wafer-Level SiP Thermal Management via Heat Pipes
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Solution Overview
Problem
Conventional integrated packages face limitations in reducing device size due to fine pitch constraints, increased processing time, and fabrication costs, as well as challenges with heat radiation and high-speed operation stability.
Innovation Solution
A system-in-package (SiP) structure is developed using a wafer-level process, where active and passive devices are integrated with a heat radiation plate and interlayer dielectrics, incorporating heat pipes and a heat sink for efficient heat dissipation, and redistribution conductive layers for electrical connectivity, allowing for high-density integration and improved thermal management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If a buried stack structure is fabricated through a sequential build-up method on a package substrate, then devices can be embedded in holes, but there is a limit in reducing the size of a device corresponding to a fine pitch
Solution Approach 1:
The patent transitions from planar integration to three-dimensional stacking by vertically stacking multiple semiconductor wafers (first wafer, second wafer, third wafer) on a substrate. This vertical dimension enables fine pitch integration without being constrained by the limitations of lateral hole formation and embedding processes, thereby reducing device size while maintaining manufacturing feasibility.
Solution Approach 2:
The patent divides the integrated package into multiple independent wafer segments (first wafer, second wafer, third wafer) that can be fabricated separately and then stacked. Each wafer can be processed independently with optimized pitch, and the final integration is achieved through vertical stacking, overcoming the fine pitch limitations of conventional buried stack methods.
2Ease of manufacture
If burying and stacking processes are performed on a package substrate by the burying and build-up method, then devices can be integrated, but time for processing and fabrication cost are increased
Solution Approach 1:
The patent performs preliminary actions by fabricating multiple wafers independently before final assembly. Each wafer is completely processed and tested separately, allowing parallel fabrication and reducing the sequential processing time required for conventional buried stack methods. The wafers are then stacked and connected, significantly reducing overall fabrication time.
Solution Approach 2:
The patent merges multiple independently fabricated wafers into a single integrated package structure. By combining separately processed wafers that have already undergone their respective fabrication processes, the method avoids the time-consuming sequential build-up and hole-filling processes, thereby reducing total processing time while maintaining integration functionality.
3Speed
If semiconductor devices for high-speed operation are embedded in a package, then high-speed operation is achieved, but heat radiation problems are raised
Solution Approach 1:
The patent extracts the heat radiation function from the embedded semiconductor devices by introducing a dedicated heat radiation plate and heat dissipation structure. The high-speed devices (CPU, GPU, etc.) are mounted on this specialized heat radiation plate that is thermally coupled to a heat sink, separating the computational function from the thermal management function and effectively solving heat radiation problems.
Solution Approach 2:
The patent introduces a heat radiation plate as an intermediary between the high-speed semiconductor devices and the heat sink. This intermediary component efficiently transfers heat from the devices to the heat sink through thermal conduction, enabling high-speed operation while maintaining effective heat radiation and preventing overheating.
4Adaptability or versatility
If conventional burying and stacking methods are used on a package substrate, then devices can be integrated, but redistribution process for electrical connection must be added due to fine pitch limits
Solution Approach 1:
The patent uses vertical stacking to achieve electrical connections between wafers through vias and conductive layers in the vertical dimension, rather than requiring complex lateral redistribution processes. The fine pitch requirements are met through vertical via formation and stacking, eliminating the need for additional redistribution processes that would increase device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of smaller, more integrated semiconductor devices with enhanced heat radiation and high-speed operation stability, reducing fabrication costs and enabling the production of slim, compact, high-performance packages.
Implementation Method 1
one or more first electronic devices mounted on the substrate by a heat radiation plate... incorporating heat pipes and a heat sink for efficient heat dissipation
Implementation Method 2
incorporating heat pipes and a heat sink for efficient heat dissipation
Data Source
AI summary
There is provided a system-in-package (SiP), which includes a substrate obtained by cutting a wafer for each unit system; one or more first electronic devices mounted on the substrate by a heat radiation plate; a plurality of interlayer dielectrics sequentially formed on the substrate; and one or more second electronic devices buried between or in the interlayer dielectrics on the substrate. A heat sink may be additionally attached to the bottom surface of the substrate. In this case, a thermal conduction path including heat pipes connecting the heat radiation plate on the substrate and the heat sink is formed. In the SiP, various types of devices are buried at a wafer level, so that a more integrated semiconductor device is implemented corresponding to demand for a fine pitch. Further, the heat radiation of a device required in high-speed operation and high heat generation is maximized due to the multi-stepped heat radiation structure, and thus the operation of the device is more stabilized.