Embedded Wafer Level Package Solder Column Through-Vias

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Solution Overview

Problem

The formation of through-vias in reconstituted wafer level packaging is hindered by the rough and pitted surfaces of molding compound layers, which interfere with the deposition of an electrically continuous seed layer, leading to higher failure rates and extended processing times.

Innovation Solution

The method involves forming a reconstituted wafer with a redistribution layer and drilling apertures to create solder columns that serve as reliable through-connections, bypassing the challenges of seed layer deposition on rough surfaces by using solder to establish electrical contact with conductive traces, and subsequent redistribution layers to ensure efficient interdie connections.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If through-vias are formed in reconstituted wafer level packaging by depositing seed layer on molding compound surface, then electrical connections can be established, but the rough and pitted surfaces of molding compound layers interfere with deposition of electrically continuous seed layer, leading to higher failure rates and extended processing times

Engineering Contradiction:

Improveseed layer continuityVSAvoidprocessing complexity

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

The patent introduces a planarization layer as an intermediary between the rough molding compound surface and the seed layer deposition process. This planarization layer provides a smooth, continuous surface that enables proper seed layer formation and subsequent electrical connections, while isolating the deposition process from the problematic rough surface topology.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent performs planarization of the molding compound surface before seed layer deposition. This preliminary action creates a suitable surface topology in advance, preventing deposition failures and reducing rework requirements, thereby improving both reliability and manufacturing efficiency.

Inventive Principle:

Principle #10Preliminary action

2Productivity

If traditional via formation processes are used on rough molding compound surfaces, then through-connections can be attempted, but processing time increases and failure rates increase

Engineering Contradiction:

Improveprocessing speedVSAvoidconnection success rate

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The planarization step is performed as a preliminary action before via formation and seed layer deposition. This pre-treatment of the surface enables subsequent processes to proceed efficiently with high success rates, avoiding rework and delays that would otherwise occur due to surface irregularities.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The planarization layer serves as a mediator that decouples the rough molding compound surface from the precision-sensitive deposition and via formation processes. This intermediary structure allows standard processing parameters to be used without compromise, maintaining both speed and reliability.

Inventive Principle:

Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables the production of reliable semiconductor packages with efficient through-connections, reducing processing time and failure rates, and allows for the stacking of multiple dies in a single package with reliable interconnections.

Implementation Method 1

releasing the vacuum while the solder is molten

Methodology Applied

Scientific EffectVacuum: Vacuum

Implementation Method 2

drawing a vacuum around the reconstituted wafer, and releasing the vacuum while the solder is molten

Methodology Applied

Scientific EffectPressure gradient: Pressure Gradient

Implementation Method 3

depositing solder paste on the second surface adjacent to the opening of each of the first plurality of apertures

Methodology Applied

Scientific EffectDeposition: Deposition (physical)

Data Source

PatentUS8916481B2Embedded wafer level package for 3D and package-on-package applications, and method of manufacture

Publication Date: 2014.12.23 STMICROELECTRONICS INT NV

AI summary

A process for manufacturing a 3D or PoP semiconductor package includes forming a redistribution layer on a reconstituted wafer, then laser drilling a plurality of apertures in the reconstituted wafer, extending from an outer surface of the reconstituted wafer to intersect electrical traces in the first redistribution layer. A solder ball is then positioned adjacent to an opening of each of the apertures. The solder balls are melted and allowed to fill the apertures, making contact with the respective electrical traces and forming a plurality of solder columns. The outer surface of the reconstituted wafer is then planarized, and a second redistribution layer is formed on the planarized surface. The solder columns serve as through-vias, electrically coupling the first and second redistribution layers on opposite sides of the reconstituted wafer.