Wafer-Level SSD Assembly Without Die Dicing or Packaging
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Solution Overview
Problem
Conventional SSD manufacturing is labor and cost intensive due to the need for multiple fabrication and assembly steps, including dicing semiconductor dies from wafers and assembling them into packages, which hinders efficient large-scale data storage solutions.
Innovation Solution
The method involves forming SSD devices from whole semiconductor wafers by creating cutouts in one wafer for electrical interconnects and bonding them with another wafer, eliminating the need for individual die dicing and packaging, and integrating SSD controllers directly onto the bonded wafers for data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional SSD manufacturing processes are used with multiple fabrication and assembly steps including dicing semiconductor dies from wafers and assembling them into packages, then reliable data storage is achieved, but manufacturing time and costs increase significantly
Solution Approach 1:
The patent merges multiple separate manufacturing operations (wafer fabrication, dicing, die assembly, packaging) into a single integrated wafer-level process. Multiple semiconductor dies are assembled and packaged simultaneously on the wafer substrate without being diced into individual pieces, thereby reducing manufacturing time while maintaining reliability through controlled wafer-level assembly processes
2Reliability
If conventional SSD manufacturing processes are used with multiple fabrication and assembly steps including dicing semiconductor dies from wafers and assembling them into packages, then reliable data storage is achieved, but manufacturing costs increase due to labor and multiple process steps
Solution Approach 1:
The patent combines multiple discrete manufacturing steps into a single wafer-level assembly process, eliminating the need for separate dicing and packaging operations for each die. This integration reduces labor requirements and process complexity, thereby lowering manufacturing costs while maintaining data storage reliability through controlled wafer-level processing
Solution Approach 2:
The wafer substrate serves multiple functions simultaneously: it acts as the mounting platform for semiconductor dies, provides electrical interconnects through through-wafer vias, and serves as the final package structure. This multi-functionality eliminates the need for separate substrate and packaging materials, reducing material costs and simplifying the manufacturing process
3Productivity
If whole semiconductor wafers are used instead of diced dies, then manufacturing time and costs are reduced, but device complexity increases due to wafer-level integration
Solution Approach 1:
The wafer is segmented into multiple functional regions during fabrication, with each region containing semiconductor dies and associated interconnect structures. Through-wafer vias are selectively formed in specific regions to provide electrical connections between dies and the substrate, allowing complex functionality to be achieved through systematic segmentation rather than monolithic design
Solution Approach 2:
Electrical interconnects in the form of through-wafer vias are formed during the wafer fabrication process before the wafer is used for die assembly. This preliminary formation of interconnect structures simplifies subsequent assembly operations, as the electrical pathways are already established and do not require complex routing during the assembly phase
4Ease of manufacture
If individual die assembly is eliminated in favor of wafer-level integration, then manufacturing steps are simplified, but precision requirements increase for wafer bonding and alignment
Solution Approach 1:
Multiple dies are assembled and bonded to the substrate simultaneously in their array positions on the wafer, eliminating the need for sequential individual die placement and alignment. This parallel assembly process simplifies manufacturing by reducing the number of discrete bonding operations, while precision is maintained through wafer-level alignment and bonding techniques that preserve relative die positions
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces manufacturing time and costs, allows for scalable storage capacity, and simplifies the SSD fabrication process by eliminating the need for individual die assembly, resulting in a more efficient and cost-effective SSD device.
Implementation Method 1
the first major surface of the first semiconductor wafer is coupled to the third major surface of the second semiconductor wafer, with the first terminal of each of the plurality of electrical interconnects bonded to a die bond pad of the plurality of die bond pads
Data Source
AI summary
A solid state drive (SSD) wafer device includes first and second semiconductor wafers coupled together. The first wafer may include a number of memory dies with die bond pads, and the second wafer may include a number of electrical interconnects, each including first and second terminals at opposed ends of the electrical interconnect. When the wafers are bonded together, the first terminals of the second wafer are bonded to the die bond pads of the memory dies of the first wafer. The second terminals are left exposed to couple with an SSD controller, which controls the transfer of data and signals between the memory dies of the first wafer and a host device such as a server in a datacenter.