Wafer-Level Stack Chip Package via Adhesive Bonding
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Solution Overview
Problem
Conventional stack type semiconductor chip packages face limitations in performance improvement and miniaturization due to indirect chip connections via bonding wires, and are unsuitable for image sensor chip packages due to sensitivity to impurity particles.
Innovation Solution
A stack type semiconductor chip package is developed using a wafer level process with a first wafer mold and a protection substrate mechanically bonded with adhesive layers, eliminating the need for bonding wires and allowing direct chip connections through vias formed in the mold layers, suitable for image sensor applications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If bonding wires are used to connect chips to PCB, then electrical connection is achieved, but package size increases and performance is limited due to indirect connection
Solution Approach 1:
The patent removes the bonding wires and PCB from the connection path between chips. Chips are directly connected to each other through vias formed in the mold layers, eliminating the intermediate connection elements (bonding wires and PCB) that increased package size and limited performance.
Solution Approach 2:
The patent transitions from planar connection (chips connected to PCB via bonding wires in the same plane) to three-dimensional stacking connection (chips connected vertically through vias in mold layers). This dimensional change enables direct chip-to-chip communication, reducing package footprint and improving performance.
2Object-affected harmful factors
If conventional packaging process is used, then chips are protected, but impurity particles contaminate image sensor chips
Solution Approach 1:
The patent performs preliminary encapsulation by forming mold layers around chips before final packaging. This preliminary encapsulation creates a protected environment that prevents impurity particle contamination during subsequent packaging processes, while maintaining chip protection through the encapsulating structure.
3Length of moving object
If vias are formed in chips for direct connection, then package miniaturization is achieved, but fabrication yield significantly decreases
Solution Approach 1:
The patent segments the via formation process from chip fabrication to packaging. Vias are formed in the mold layers during the packaging process rather than in the chips themselves. This segmentation allows chips to be fabricated with standard processes (maintaining high yield) while still achieving miniaturization through vias in the packaging structure.
Solution Approach 2:
The patent introduces mold layers as intermediary structures that contain the vias. Instead of forming vias directly in chips (which reduces yield), the mold layers serve as mediators that provide the via structure needed for miniaturization without compromising chip fabrication quality.
4Reliability
If interposer chip is used for direct connection, then performance improves, but device complexity and fabrication difficulty increase
Solution Approach 1:
The patent makes the mold layers multi-functional: they serve both as encapsulating material protecting the chips and as the structural medium containing the vias for electrical connection. This eliminates the need for separate interposer chips, reducing device complexity while maintaining direct connection performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances package performance, miniaturization, and fabrication yield while preventing contamination from impurity particles, making the package suitable for image sensor applications.
Implementation Method 1
a first adhesive layer interposed therebetween, and mechanically bonded with the first wafer mold
Data Source
AI summary
A stack type semiconductor chip package includes a first wafer mold, a protection substrate, and a second wafer mold that are stacked in a wafer level process. The first wafer mold includes a first chip having first pads and a first mold layer encapsulating the first chip. The protection substrate is placed on the first wafer mold, is mechanically bonded with the first wafer mold using a first adhesive layer, and includes wiring layers facing the first pads. The second wafer mold is placed under the first wafer mold, is mechanically bonded with the first wafer mold using a second adhesive layer, and includes a second chip having second pads, and a second mold layer encapsulating the second chip. First vias electrically connect the wiring layers of the protection substrate with the second pads. Second vias electrically connect the wiring layers of the protection substrate with external connection terminals.