Wafer-Level Stack Package Through-Electrode Manufacturing
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Solution Overview
Problem
The manufacturing yield of stack packages decreases due to thermal fatigue and poor initial semiconductor chip yields in existing stacking techniques, particularly when using through-electrodes, as they require complex processes and can cause semiconductor chip degradation.
Innovation Solution
A method for manufacturing a wafer-level stack package involves back-grinding a wafer, attaching a support member, stacking good semiconductor chips, forming through-electrodes, attaching additional chips with re-distribution lines, and sawing to a chip level, thereby reducing process complexity and avoiding thermal stress.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through-electrodes are used to stack semiconductor chips, then electrical connection between chips is achieved and signal transmission path is shortened, but manufacturing yield decreases due to thermal fatigue and process complexity
Solution Approach 1:
The patent performs preliminary selection and stacking of only good semiconductor chips at the wafer level before forming through-electrodes. This preliminary action ensures that only functional chips are stacked together, preventing yield loss from defective chips and avoiding thermal fatigue issues that would occur with rework or replacement of defective chips after stacking.
Solution Approach 2:
The patent segments the manufacturing process into distinct stages: wafer-level stacking of good chips first, then through-electrode formation, and finally sawing into individual packages. This segmentation allows yield determination to occur at the wafer level before irreversible through-electrode formation, isolating the high-yield stacking operation from the complex through-electrode process.
2Volume of moving object
If through-electrodes are formed to connect stacked chips, then package size is reduced and signal path is shortened, but process complexity increases leading to manufacturing difficulties
Solution Approach 1:
The patent performs preliminary stacking of semiconductor chips at the wafer level before forming through-electrodes. This preliminary action simplifies the overall process by establishing the chip stack configuration early, allowing subsequent through-electrode formation to be performed on a stable, pre-assembled structure rather than requiring complex alignment and assembly operations.
Solution Approach 2:
The patent merges multiple operations into the wafer-level process: chip selection, stacking, and initial alignment are combined into a single wafer-level operation before through-electrode formation. This merging reduces the number of separate complex steps needed and allows the use of standard wafer processing equipment for the stacking operation.
3Strength
If soldering is used to stack semiconductor chips, then mechanical and electrical connection is achieved, but thermal stress causes degradation in semiconductor chips
Solution Approach 1:
The patent extracts the harmful thermal stress element from the chip stacking process by replacing soldering with a low-temperature bonding method. The semiconductor chips are bonded at temperatures below their degradation threshold, and the through-electrodes are formed separately through a different process that does not subject the chips to repeated thermal cycling, thereby eliminating thermal fatigue degradation.
Solution Approach 2:
The patent introduces an intermediary bonding process that mechanically connects the chips without requiring high-temperature soldering. This intermediary method uses low-temperature bonding to join chips, and the through-electrodes serve as the primary electrical connection medium rather than relying on solder joints, thereby protecting the chips from thermal stress while maintaining electrical connectivity.
Data Source
AI summary
Manufacturing a wafer level stack package includes the steps of back-grinding a lower surface of a wafer including a plurality of first semiconductor chips. A support member is attached to a lower surface of the back-grinded wafer. One or more second semiconductor chips are stacked on the respective first semiconductor chips of the back-grinded wafer. First through-electrodes are formed to electrically connect the stacked first semiconductor chips and second semiconductor chips. Third semiconductor chips are attached to uppermost ones of the stacked second semiconductor chips, and the third semiconductor chips have second through-electrodes which are electrically connected to the first through-electrodes and re-distribution lines which are connected to the second through-electrodes. Outside connection terminals are attached to the re-distribution lines of the third semiconductor chips. The first semiconductor chips of a wafer level on which the second and third semiconductor chips are stacked are sawed to for semiconductor packages at a chip level.