Wafer Level Stack Structure for System-in-Package
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Solution Overview
Problem
Current semiconductor packaging technologies are limited to chip-level stacking, preventing the application of Wafer-Level Chip-Scale Package (WLCSP) technology in System-in-Package (SIP) systems, which restricts size reduction, cost-effectiveness, and thermal conduction enhancements.
Innovation Solution
A wafer level stack structure is developed by stacking wafers with device chips of different types, each with a specific number of I/O pads, and coupling them using vias and connection bumps for electrical and thermal connections, allowing for a system-in-package configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If chip-level stacking is used, then electrical connectivity is achieved, but size reduction and cost-effectiveness are limited
Solution Approach 1:
The patent transitions from conventional chip-level stacking to wafer-level stacking, moving the integration process to a higher dimensional level (wafer level rather than chip level). This enables multiple device chips to be stacked and connected before packaging, achieving size reduction while maintaining manufacturing feasibility through wafer-level processing techniques.
Solution Approach 2:
The patent performs electrical connection formation between device chips at the wafer level before the chips are separated and packaged individually. This preliminary action of creating inter-chip connections at the wafer stage enables subsequent size reduction and simplifies final packaging, as the complex electrical interconnections are already established.
2Volume of moving object
If wafer-level stacking is implemented, then size reduction is achieved, but manufacturing complexity increases
Solution Approach 1:
The patent segments the wafer into multiple device chips that can be stacked vertically. Each device chip is processed and prepared separately at the wafer level, then stacked in a controlled manner. This segmentation approach manages structural complexity by breaking down the complex stacking process into manageable segments while achieving compact three-dimensional integration.
Solution Approach 2:
The patent creates a universal wafer-level stacking platform that can accommodate different types of device chips with varying numbers of I/O pads. The same wafer-level processes and structures are used regardless of the specific device chip type, enabling multi-functionality and reducing overall manufacturing complexity despite the diversity of stacked components.
3Adaptability or versatility
If diverse device chips are integrated at chip level, then functionality is enhanced, but alignment and connection difficulty increase
Solution Approach 1:
The patent moves diverse device chip integration from chip level to wafer level, where alignment and connection processes benefit from the larger wafer-scale platform. This dimensional change provides better mechanical support and alignment references, enabling precise integration of device chips with different I/O pad configurations while enhancing overall functionality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables more efficient heat dissipation and electrical connectivity, reduces production costs, and enhances the performance of semiconductor devices by allowing for the integration of diverse chips at the wafer level, overcoming the limitations of conventional chip-level stacking.
Implementation Method 1
enhances thermal conduction characteristics
Implementation Method 2
electrical connections to allow signal and power access to and from the chip
Data Source
AI summary
A method of forming a wafer level stack structure, including forming a first wafer including a first device chip, wherein the first device chip includes a plurality of input/output (I/O) pads, forming a second wafer including a second device chip, wherein each second device chip contains a second plurality of I/O pads, the second device chip is approximately equal in size to the first chip size, stacking the first wafer and the second wafer, and coupling the first wafer and the second wafer to each other. A method of forming a system-in-package for containing a wafer level stack structure, including forming a wafer level stack structure including a first device chip having a first plurality of input/output (I/O) pads and a second device chip having a second plurality of I/O pads, and forming a common circuit board to which the wafer level stack structure is connected.