Wafer-Level Stacked Semiconductor Die Assembly
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Solution Overview
Problem
Existing semiconductor die assembly technologies face challenges in achieving high circuit density and efficient packaging, particularly in stacked die configurations, which often result in increased thickness and complexity, limiting throughput and increasing costs.
Innovation Solution
The method involves stacking semiconductor dice on an intact wafer, using conductive elements to connect the dice vertically, and encapsulating them with a dielectric material to provide mechanical support and protection, allowing for wafer-level processing and singulation, thereby reducing thickness and cost while enabling higher throughput and accurate step sizes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional stacked die assembly methods are used, then circuit density is improved, but package thickness increases and manufacturing complexity increases
Solution Approach 1:
The patent transitions from planar die arrangement to vertical stacking configuration, utilizing the third dimension (height) to increase circuit density. Multiple semiconductor dies are stacked vertically and interconnected through conductive vias, transforming the two-dimensional layout into a three-dimensional structure that achieves higher density without proportionally increasing package thickness.
Solution Approach 2:
The patent implements nested interconnection structures where conductive vias are formed through multiple die layers, with each via nesting through subsequent dies. The underfill material nests around the conductive interconnects, and the entire stack is encapsulated within a protective package structure, creating concentric nested layers that optimize space utilization.
2Quantity of substance
If conventional stacked die assembly methods are used, then circuit density is improved, but device complexity increases
Solution Approach 1:
The patent performs preliminary formation of conductive vias and interconnection structures on each semiconductor die before stacking. The underfill material is pre-applied to the bottom die, and conductive pathways are pre-established through vias. This preliminary preparation simplifies the subsequent stacking process by eliminating the need for complex post-assembly interconnection formation.
Solution Approach 2:
The patent introduces underfill material as an intermediary substance between the stacked dies. This underfill serves multiple functions: it provides mechanical support and alignment during stacking, fills voids between dies, and facilitates thermal management. The intermediary underfill simplifies the assembly process by enabling self-alignment and reducing the need for precision positioning mechanisms.
3Productivity
If wafer-level processing is used, then manufacturing throughput is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent implements self-aligning features where the underfill material automatically flows to fill gaps and align the stacked dies during the wafer-level processing. The viscous underfill serves as a self-correcting mechanism that compensates for minor misalignments, eliminating the need for complex external alignment systems and maintaining high precision throughout high-volume manufacturing.
Data Source
AI summary
Methods of fabricating multi-die assemblies including a base semiconductor die bearing a peripherally encapsulated stack of semiconductor dice of lesser lateral dimensions, the dice vertically connected by conductive elements between the dice, resulting assemblies, and semiconductor devices comprising such assemblies.