Wafer Level IC Packaging with Stacked Circuits and Reduced Footprint
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Solution Overview
Problem
Current integrated circuit packaging technologies face challenges in reducing package dimensions, cost, and increasing functionality while maintaining connectivity and performance, as they struggle to efficiently integrate more circuits into smaller spaces with existing manufacturing methods.
Innovation Solution
The method involves forming a partially removed region on a leadframe, mounting integrated circuits with adhesives, and creating interconnection layers to connect the circuits and peripheral leads, allowing for the stacking of multiple circuits within a reduced package size without through vias, thereby reducing package size and manufacturing complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If existing manufacturing processes are reused, then manufacturing cost is reduced, but package dimensions cannot be reduced
Solution Approach 1:
The patent transitions from planar circuit layout to three-dimensional stacked configuration, allowing multiple circuits to be vertically integrated. This dimensional change enables reduced package footprint while maintaining manufacturing compatibility with existing processes.
Solution Approach 2:
Multiple integrated circuits are nested vertically within a single package structure, with each circuit stacked above the other. This nesting approach maximizes space utilization and reduces overall package dimensions while using standard manufacturing techniques.
2Adaptability or versatility
If more integrated circuits are integrated into each circuit, then functionality is increased, but package size reduction is not achieved
Solution Approach 1:
Instead of increasing functionality within a single planar circuit layer, the patent stacks multiple circuit layers vertically. This enables higher functionality density while reducing the horizontal package footprint by utilizing the vertical dimension.
Solution Approach 2:
The stacked package structure provides a universal platform that can accommodate different types and configurations of integrated circuits. Each stack position can be configured for different functions, enabling multi-functionality within a compact form factor.
3Adaptability or versatility
If circuits are stacked into a single package, then more functions are achieved, but height and space reduction requirements are not fully met
Solution Approach 1:
The patent employs thin interconnection layers and compact bonding structures between stacked circuits, minimizing the vertical space required for each circuit layer. This reduces overall package height while maintaining functional integrity.
Solution Approach 2:
Interconnection structures are pre-formed and integrated during the stacking process rather than added afterward. This preliminary integration of interconnects reduces the additional height that would be required for separate interconnection layers.
Data Source
AI summary
A method of manufacture of an integrated circuit packaging system includes: removing a portion of a leadframe to form a partially removed region and an upper portion of a peripheral lead on the leadframe first side; mounting a first integrated circuit over the partially removed region with a first adhesive; forming a first molding layer directly on the first integrated circuit and the peripheral lead; removing a portion of a leadframe second side exposing the first adhesive; mounting a second integrated circuit on the first adhesive of the first integrated circuit; forming a first interconnection layer directly on the first integrated circuit with the first integrated circuit and the peripheral lead electrically connected; and forming a second interconnection layer directly on the second integrated circuit with the second integrated circuit and the peripheral lead electrically connected.