Wafer-Level Semiconductor Packages With Stacked Connecting Elements
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Solution Overview
Problem
Conventional wafer-level packaging is inadequate for increasing semiconductor device density within a limited footprint, as it restricts components to a specific periphery and cannot accommodate the growing complexity and functionality of semiconductor devices.
Innovation Solution
The development of wafer-level semiconductor device packages with stacking functionality, which includes a redistribution unit, stacked semiconductor devices, connecting elements, and a package body that allows for a fan-out configuration, enabling components to be disposed both within and outside the periphery of the semiconductor device, and a manufacturing method that involves stacking, molding, and wire-bonding to achieve higher device density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional wafer-level packaging is used with fan-in configuration, then manufacturing process is simple, but device density and functionality are limited
Solution Approach 1:
The patent transitions from conventional planar fan-in configuration to a three-dimensional stacked configuration. Multiple semiconductor devices are stacked vertically with redistribution units positioned between them, enabling fan-out connectivity. This dimensional change allows electrical contacts to be disposed both within and outside the periphery of the semiconductor device, significantly increasing device density while maintaining manufacturing feasibility through wafer-level processing.
2Area of moving object
If semiconductor device size is reduced, then footprint area is minimized, but device functionality becomes limited
Solution Approach 1:
The patent implements a nested structure where multiple semiconductor devices are stacked vertically within a compact footprint. Each device is nested between redistribution units that provide electrical interconnections. This nesting approach allows multiple functional layers to coexist in a small area, enabling complex functionality while minimizing the overall package footprint.
3Adaptability or versatility
If fan-out configuration is implemented with components outside periphery, then device functionality is enhanced, but manufacturing complexity increases
Solution Approach 1:
The patent performs preliminary actions by forming redistribution units and electrical interconnections at the wafer level before singulation. The redistribution units are created on the wafer surface, and electrical contacts are established between stacked devices while still in wafer form. This preliminary manufacturing approach simplifies the overall process compared to post-singulation assembly, as it leverages the precision and efficiency of wafer-level processing techniques.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution allows for a higher density of semiconductor devices within a given footprint area, accommodating increased complexity and functionality while providing mechanical stability and environmental protection, thus addressing the limitations of conventional packaging.
Implementation Method 1
a second connecting element including a second upper end that is wire-bonded to the second active surface of the second semiconductor device
Data Source
AI summary
Described herein are wafer-level semiconductor device packages with stacking functionality and related stacked package assemblies and methods. In one embodiment, a semiconductor device package includes a set of connecting elements disposed adjacent to a periphery of a set of stacked semiconductor devices. At least one of the connecting elements is wire-bonded to an active surface of an upper one of the stacked semiconductor devices.