Wafer-Level Stacking with Edge Traces for Thin Packages
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Solution Overview
Problem
Conventional stacked microelectronic packages face challenges with complexity, cost, thickness, and testability, necessitating the development of reliable, thin, and economically manufactured wafer-scale packages.
Innovation Solution
A method involving the stacking of microelectronic elements with traces extending to their edges, forming notches to expose these traces, and creating leads at the notch sidewalls for electrical contacts, while using adhesives to support and insulate the traces, and optionally incorporating a substrate with relief cavities to prevent cracking during processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional stacked microelectronic packages are used, then multiple chips can be stacked within a package to reduce surface area, but the package complexity increases and testability decreases
Solution Approach 1:
The patent transitions from planar packaging to three-dimensional wafer stacking, where multiple wafers are bonded vertically to each other. This dimensional change allows multiple chips to occupy the same footprint area while maintaining simplified interconnections through vertical alignment, thus reducing package surface area without proportionally increasing complexity
Solution Approach 2:
The patent creates a universal wafer-level packaging platform where the same bonding and interconnection processes can be applied to stack multiple identical or different types of microelectronic wafers. This multi-functional approach allows the system to handle various chip types through standardized procedures, reducing overall package complexity while enabling multiple chips per package
2Area of stationary object
If conventional stacked microelectronic packages are used, then multiple chips can be stacked within a package to reduce surface area, but testability becomes more difficult
Solution Approach 1:
The patent performs wafer-level testing and characterization before the stacking process, and includes test structures that remain accessible after bonding. By conducting preliminary tests on individual wafers and incorporating accessible test points in the stacked configuration, the system maintains testability despite the three-dimensional arrangement, avoiding the need to disassemble the stack for testing
3Length of stationary object
If wafer level processing is used to produce thinner packages, then manufacturing cost decreases and package thickness reduces, but reliability challenges arise
Solution Approach 1:
The patent replaces traditional mechanical wire bonding with direct wafer-to-wafer bonding using copper traces and conductive adhesives. This substitution eliminates mechanical stress points associated with wire bonds and creates more robust electrical connections that better withstand thermal cycling and mechanical loads, thereby improving reliability while enabling thinner package profiles
Solution Approach 2:
The patent employs composite material structures including copper trace patterns on dielectric layers, combined with conductive adhesive formulations that provide both electrical connection and mechanical bonding. This composite approach creates interfaces that are simultaneously electrically conductive and mechanically strong, addressing reliability concerns in thin wafer-stack packages
4Ease of manufacture
If wafer level processing is used to produce thinner packages, then manufacturing cost decreases, but manufacturing precision requirements increase
Solution Approach 1:
The patent incorporates self-aligning features such as registration marks, interdigitated trace patterns, and complementary geometric structures on opposing wafer surfaces. These features automatically guide wafer alignment during the bonding process, reducing the need for high-precision external alignment equipment and procedures, thereby maintaining manufacturing precision while controlling costs
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in thinner, more reliable, and cost-effective stacked microelectronic packages with enhanced electrical performance, allowing for efficient wafer-level processing and potential for further stacking and interconnection.
Implementation Method 1
using adhesives to support and insulate the traces
Data Source
AI summary
In accordance with an aspect of the invention, a stacked microelectronic package is provided which may include a plurality of subassemblies, e.g., a first subassembly and a second subassembly underlying the first subassembly. A front face of the second subassembly may confront the rear face of the first subassembly. Each of the first and second subassemblies may include a plurality of front contacts exposed at the front face, at least one edge and a plurality of front traces extending about the respective at least one edge. The second subassembly may have a plurality of rear contacts exposed at the rear face. The second subassembly may also have a plurality of rear traces extending from the rear contacts about the at least one edge. The rear traces may extend to at least some of the plurality of front contacts of at least one of the first or second subassemblies.