Wafer-Level Data Storage Integrating Memory and Controller
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Solution Overview
Problem
Current data storage systems face performance limitations and high development costs due to the use of PCBs and individually packaged memory packages, which require complex signal paths and lengthy development times to comply with traditional form factors and interfaces.
Innovation Solution
A data storage system utilizing a wafer as the physical and electrical substrate, eliminating the need for PCBs and individual packaging by integrating memory cells and controllers directly on the wafer, with existing wafer-scale technologies like bumping, RDL, and TSV for connections, allowing for higher performance and reduced costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If PCBs and individual memory packages are used, then compatibility with traditional form factors and interfaces is maintained, but device complexity and development time increase
Solution Approach 1:
The patent merges multiple separate components (memory dies, PCB, connectors, housing) into a single integrated wafer-level package. The wafer serves as both the substrate and the complete storage device, eliminating the need for separate PCB and individual packaging, thus reducing system complexity while maintaining external compatibility.
Solution Approach 2:
The wafer is designed to perform multiple functions simultaneously: it serves as the memory array substrate, the interconnect structure, the package body, and the interface connector. This multi-functionality eliminates the need for separate components and reduces overall system complexity while maintaining compatibility with traditional interfaces.
2Adaptability or versatility
If PCBs and individual memory packages are used, then traditional interfaces are supported, but manufacturing complexity and development costs increase
Solution Approach 1:
The patent combines multiple manufacturing steps and components into a single wafer-level fabrication process. Memory dies are fabricated, tested, and packaged together on the wafer using existing wafer-scale technologies, eliminating the need for separate PCB assembly and individual packaging operations, thus simplifying manufacturing.
Solution Approach 2:
The patent changes the scale and integration level of manufacturing from individual die packaging to wafer-level processing. By utilizing existing wafer-scale technologies such as bumping, RDL, and TSV, the manufacturing process achieves higher integration while maintaining compatibility with traditional interfaces, reducing both complexity and cost.
3Adaptability or versatility
If signal paths are extended through PCBs and connectors, then traditional interfaces are maintained, but signal integrity and performance deteriorate
Solution Approach 1:
The patent extracts and eliminates the PCB and intermediate connectors from the signal path, maintaining only the essential interface functionality at the wafer level. This shortens the signal path and removes potential sources of signal degradation while preserving compatibility with traditional interfaces through direct wafer-to-connector coupling.
4Adaptability or versatility
If multiple PCB layers and components are used, then functionality is achieved, but material usage and cost increase
Solution Approach 1:
The patent merges multiple functional layers and components into a single wafer structure. The wafer integrates the memory array, interconnects, and package structure, eliminating the need for multiple PCB layers and separate components, thus reducing material usage while maintaining full system functionality.
Data Source
AI summary
A data storage system is described that uses wafer-level packaging. In one embodiment an apparatus includes a silicon wafer, a plurality of memory cells formed directly on the wafer, an encapsulant formed over the memory cells, a plurality of wiring connections to connect the memory cells to an external interface, a memory controller, and an external interface.