Wafer-Level System Testing via Emulator Coupling
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Solution Overview
Problem
The lengthy process of semiconductor testing, which can take weeks or months, delays the identification of faulty devices and increases costs due to the separation and packaging of devices before system-level testing, leading to potential defects in larger electronic devices.
Innovation Solution
Perform system-level testing on processing devices still incorporated in a silicon wafer by electrically coupling an emulator system that models the intended system, allowing software execution and functionality testing before separation and packaging.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If devices are separated and packaged before system-level testing, then devices can be individually handled and tested, but testing duration increases to weeks or months and costs increase
Solution Approach 1:
The patent applies preliminary action by performing system-level testing on devices while they are still incorporated in the silicon wafer, before separation and packaging. The emulator system is coupled to the wafer to enable software execution and functionality testing early in the manufacturing process, identifying defects before devices are packaged. This resolves the contradiction by eliminating the need to wait until after packaging for system-level testing, significantly reducing testing duration while still enabling individual device evaluation through the wafer-level access mechanism.
2Ease of operation
If devices are separated and packaged before system-level testing, then devices can be individually handled, but defective devices cannot be identified earlier leading to wasted expense
Solution Approach 1:
The patent implements preliminary action by conducting system-level testing before device separation and packaging. The emulator system enables early detection of defective devices while they are still on the wafer, allowing manufacturers to identify and remove defective devices before packaging. This prevents wasted expense on packaging and distributing defective devices, as defects are detected early in the manufacturing process when only the wafer processing has been completed.
3Reliability
If system-level testing is performed after packaging, then software can be tested on packaged devices, but software modifications cannot be accelerated
Solution Approach 1:
The patent applies preliminary action by enabling system-level testing and software execution while devices are still incorporated in the silicon wafer, before packaging is completed. The emulator system provides a platform for executing software and identifying defects early, allowing software modifications to be accelerated to an earlier point in the production process. This resolves the contradiction by enabling software functionality verification before packaging, thereby accelerating the software development cycle while maintaining reliable testing of packaged devices.
4Loss of time
If emulator system is coupled to silicon wafer, then system-level testing can be performed early, but device complexity increases
Solution Approach 1:
The patent applies universality by designing the emulator system to serve multiple functions: it models the intended system environment, enables software execution, provides for system-level testing, and facilitates defect identification all while coupling to the silicon wafer. This multi-functional approach resolves the contradiction by consolidating multiple testing and verification capabilities into a single integrated system, reducing overall testing duration without proportionally increasing complexity.
Data Source
AI summary
This document describes apparatuses, systems, and techniques for performing system-level testing on a processing device incorporated while the device is still incorporated within a silicon wafer by electrically coupling an emulator system to the silicon wafer. For example, an apparatus includes a wafer interface configured to engage contacts on a silicon wafer for a selected processing device of a plurality of processing devices incorporated within the silicon wafer. A emulator system is operatively coupled to the wafer interface to electrically engage the contacts for the selected processing device and to model a computing device in which the selected processing device will be used. The emulator system includes components enabling the selected processing device to access and execute software via the emulator system to test functionality of the selected processing device in executing the software without the selected processing device being divided from others of the plurality of processing devices.