Wafer-Level Integration Using Tapered Vias
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Solution Overview
Problem
The challenge in semiconductor manufacturing lies in forming appropriate electrical connections between wafers with differing functionalities and varying contact pad locations, which complicates the integration of high-density, high-speed integrated circuits with small footprints.
Innovation Solution
The method involves forming conductive adhesive bonds between wafers with bond pads, creating interconnect structures through vias and metal layers within the wafers, and stacking additional wafers to establish electrical connections, allowing for the integration of multiple wafers with varying functionalities into a single semiconductor package.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional wafer bonding methods are used to connect wafers with differing functionalities and varying contact pad locations, then electrical connections can be established, but the package footprint increases and manufacturing complexity increases
Solution Approach 1:
The patent transitions from planar wafer arrangement to three-dimensional stacking architecture. Multiple wafers are bonded vertically together with interconnect structures extending through the stack, enabling high-density integration in the vertical dimension while maintaining a compact footprint. The interconnect structures include vias that penetrate through wafer thickness to establish electrical connections between stacked devices.
2Adaptability or versatility
If conventional wafer bonding methods are used to connect wafers with differing functionalities and varying contact pad locations, then electrical connections can be established, but device complexity increases
Solution Approach 1:
The patent implements preliminary alignment and bonding of wafers before final packaging. Wafer-level interconnect structures are formed and aligned during the bonding process itself, rather than requiring post-bonding adjustments. This preliminary action at the wafer level simplifies subsequent packaging operations and reduces overall manufacturing complexity despite the advanced functionality being integrated.
3Speed
If direct electrical connections between wafers are established, then circuit performance improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent introduces intermediary interconnect structures including conductive vias and bonding pads that facilitate electrical connections between stacked wafers. These intermediaries provide tolerance for alignment variations while maintaining low-inductance, high-speed electrical paths. The interconnect structures act as buffers that accommodate manufacturing variations without compromising the high-performance electrical connections.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of high-density, high-speed semiconductor packages with a small footprint by facilitating direct and short electrical connections between wafers, enhancing circuit performance and reducing manufacturing costs.
Implementation Method 1
connecting the bond pads of the first and second wafers using a conductive adhesive
Data Source
AI summary
A semiconductor device has first and second wafers having bond pads. The bond pad of the second wafer is connected to the bond pad of the first wafer using a conductive adhesive. A first interconnect structure is formed within the second wafer and includes a first via formed in a back surface of the second wafer to expose the bond pad of the second wafer. A first metal layer is formed conformally over the first via and is in electrical contact with the bond pad of the second wafer. A third wafer is mounted over the second wafer by connecting a bond pad formed over a front surface of the third wafer to the first metal layer. A second interconnect structure is formed over a backside of the third wafer opposite the front surface. The second interconnect structure is electrically connected to the first metal layer.