Wafer-Level Test Adjacent Semiconductor Die Using mBIST and Scribe Lines
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Solution Overview
Problem
The alignment of probe needles in wafer-level testing of semiconductor devices becomes increasingly difficult due to the shrinking size of terminals, leading to misalignment issues that can cause incorrect contact, improper contact, or failure to contact targeted pins, resulting in unnecessary failure of devices and reduced production efficiency and increased costs.
Innovation Solution
The implementation of built-in self-test circuitry (mBIST) and scribe lines that connect terminals of adjacent semiconductor dies, allowing for simplified test setup and reduced test time by enabling parallel testing and interconnection of multiple dies, with supplemental mBIST circuitry for additional functionality and efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional probe needle alignment methods are used for wafer-level testing, then testing can be performed on multiple devices in parallel, but alignment difficulty increases and misalignment occurs due to shrinking terminal sizes
Solution Approach 1:
The patent introduces an intermediary alignment mark structure that mediates between the probe needle positioning system and the shrinking terminal structures. This alignment mark serves as a reference intermediary that allows the probe needle system to maintain accurate positioning despite the reduced scale of terminal features, thereby enabling parallel testing while preserving alignment precision
Solution Approach 2:
The patent implements preliminary alignment mark formation and verification steps before the actual probe needle contact testing. By pre-establishing reference alignment features on the wafer, the system prepares the positioning infrastructure in advance, allowing subsequent parallel testing to proceed with maintained precision across multiple devices
2Device complexity
If probe needles are misaligned due to shrinking terminal sizes, then testing setup becomes more difficult, but device yield and production efficiency decrease
Solution Approach 1:
The alignment mark structure acts as a mediator that simplifies the test setup process by providing a clear reference target for probe needle positioning. This intermediary reference system reduces the complexity of aligning probe needles with shrinking terminal features, thereby maintaining device yield despite increased terminal miniaturization
Solution Approach 2:
The system employs self-alignment mechanisms where the alignment marks and probe needle positioning system work together autonomously to achieve proper registration. This self-service alignment approach reduces the need for complex manual adjustment procedures, simplifying test setup while preserving reliable device testing and yield
Data Source
AI summary
Wafer-level testing of multiple adjacent semiconductor die of a semiconductor wafer in parallel using built-in self-test circuitry for a memory (mBIST) and scribe lines that connect certain terminals of a semiconductor die to terminals of an adjacent semiconductor die. During the wafer-level testing, probe needles of a test setup connect to a single one of the multiple adjacent semiconductor die, and mBIST commands are passed from the single one of the multiple adjacent semiconductor die to one or more adjacent semiconductor die. In some examples, the scribe lines connect mBIST circuit terminals of one semiconductor die to mBIST circuit terminals of an adjacent semiconductor die. In some examples, the scribe lines connect I/O terminals of one semiconductor die to I/O terminals of an adjacent semiconductor die. The scribe lines may cross scribe regions of the wafer to connect the respective terminals of the adjacent semiconductor die.