Wafer-Level Test Module for Image Sensor Chips
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Solution Overview
Problem
Current wafer-level test systems for image sensor chips are inefficient and time-consuming due to the need for repeated calibration and difficulty in aligning optical axes of large lenses with micro-sized image capturing devices, limiting the ability to accurately and rapidly test multiple image sensor chips on an integrated circuit wafer.
Innovation Solution
A wafer-level test module comprising a base layer, an optical layer, and a cover layer, where multiple apertures and optical lenses are precisely aligned to focus test light onto each image sensor chip, allowing for simultaneous and accurate testing of multiple chips with minimal calibration, using a probe card with a detection zone and circuit zone for electrical connection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional lens sets with large optical lenses are used to cover multiple image sensor chips, then the coverage area is increased, but the optical axis alignment precision deteriorates due to the difficulty of aligning large lenses with micro-sized image capturing devices
Solution Approach 1:
The patent divides the single large lens system into multiple smaller optical lenses, each corresponding to one image sensor chip. This segmentation allows each small lens to be precisely aligned with its corresponding micro-sized image capturing device, solving the alignment precision problem while maintaining coverage of multiple chips through the multi-lens array configuration
Solution Approach 2:
Each optical lens in the array is optimized for its specific local position and corresponds to a specific image sensor chip. This local optimization ensures that each lens-chip pair achieves optimal optical alignment and performance, rather than using a single large lens that must compromise across multiple positions
2Manufacturing precision
If repeated calibration procedures are performed to align optical axes with image capturing devices, then the optical alignment precision is improved, but the testing time increases significantly
Solution Approach 1:
The patent incorporates alignment marks and positioning structures directly into the probe card design during manufacturing. This preliminary action allows the optical lenses to be pre-aligned with the image sensor chips before actual testing begins, eliminating the need for repeated calibration procedures during the testing process and significantly reducing testing time
3Adaptability or versatility
If a probe card with integrated lens set is used for wafer-level testing, then the testing capability is provided, but the device complexity increases due to the integration of optical components
Solution Approach 1:
The probe card is designed with multi-functionality, serving both as an electrical testing interface and an optical testing platform. The same probe card structure accommodates both electrical probes and optical lenses, allowing a single device to perform multiple testing functions without requiring separate specialized equipment, thereby managing complexity while enhancing versatility
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables rapid and accurate wafer-level testing of multiple image sensor chips by optimizing the alignment and projection of test light, reducing the need for repeated calibration and improving the precision of optical axis alignment, thus enhancing the efficiency of the testing process.
Implementation Method 1
multiple optical lenses 34 respectively corresponding to the image capturing devices 6a, which optical lenses are used to focus the test light 7 onto the image capturing devices 6a
Data Source
AI summary
A wafer-level test module is disclosed to include a base layer having multiple first apertures spaced from one another at a pitch corresponding to the pitch of the image sensor chips of an integrated circuit wafer, a cover layer having second apertures respectively axially aimed at the first apertures, and an optical layer sandwiched between the base layer and the cover layer having multiple optical lenses of which the optical axes pass through the first apertures and the second apertures, so that when one image capturing device of the image sensor chips of an integrated circuit wafer is adjusted to the image plane of one of the optical lenses and the wafer-level test module is set in alignment with the integrated circuit wafer horizontally and vertically, then the effective test light can be simultaneously projected onto the image capturing devices of the respective image sensor chips through the wafer-level test module to achieve an effective wafer-level test on multiple image sensor chips of the integrated circuit wafer accurately and rapidly.