Wafer Logic Region Defect Detection via Super-Region Merging
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Solution Overview
Problem
Current defect detection methods in semiconductor manufacturing face challenges with high numbers of design-based care areas, leading to impractical throughput and cost issues due to increased sensitivity regions, which can result in lower performance and more noise in inspection processes.
Innovation Solution
The system organizes sub-regions into super-regions for defect detection, using a computer subsystem to assign and generate scatter plots with different segmentation values for each type of sub-region, allowing for efficient defect detection across a logic region on a wafer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the number of design-based care areas is increased to improve defect detection sensitivity, then measurement precision is improved, but productivity deteriorates due to impractical throughput and cost issues
Solution Approach 1:
The patent combines multiple sub-regions into a single super-region, allowing multiple sensitivity regions to be processed together in one inspection pass. This merging approach maintains the sensitivity benefits of multiple care areas while improving throughput by reducing the number of separate processing operations required.
2Measurement precision
If the number of design-based care areas is increased to improve defect detection sensitivity, then measurement precision is improved, but device complexity worsens due to increased processing complexity
Solution Approach 1:
The patent merges multiple sub-regions into a super-region, reducing the overall processing complexity. By handling multiple sensitivity regions within a single super-region framework, the system simplifies the processing architecture while preserving the ability to detect defects with high sensitivity across multiple areas.
3Measurement precision
If design-based care areas are reduced in size to increase inspection frequency across the wafer, then measurement precision is improved, but productivity worsens due to impractical throughput requirements
Solution Approach 1:
The patent combines multiple smaller sub-regions into a super-region, enabling the system to process fine-grained sensitivity regions without the throughput penalty of processing each separately. This allows high inspection sensitivity across the wafer while maintaining practical processing speeds by batch-processing multiple regions together.
Data Source
AI summary
Methods and systems for detecting defects in a logic region on a wafer are provided. One method includes acquiring information for different types of design-based care areas in a logic region of a wafer. The method also includes designating the different types of the design-based care areas as different types of sub-regions and, for a localized area within the logic region, assigning two or more instances of the sub-regions located in the localized area to a super-region. In addition, the method includes generating one scatter plot for all of the two or more instances of the sub-regions assigned to the super-region. The one scatter plot is generated with different segmentation values for the output corresponding to the different types of the sub-regions. The method further includes detecting defects in the sub-regions based on the one scatter plot.