Wafer Carrier Lot Combination for Semiconductor Throughput
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Solution Overview
Problem
Integrated circuit fabrication lines face inefficiencies due to partially filled wafer carriers, as some equipment cannot process these at the same rate as full carriers, leading to reduced productivity and increased wait times.
Innovation Solution
A process is implemented to identify compatible partial lots, combine them into a single wafer carrier, and synchronize their processing through sequential steps, with a multi-lot verification process to ensure all wafers complete each step without exceeding maximum allowable wait times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If partial lots are processed separately in partially filled wafer carriers, then flexibility in handling customer orders and wafer scrubs is improved, but productivity and wafer throughput deteriorate due to reduced processing rates
Solution Approach 1:
The patent combines multiple partial lots into a single wafer carrier to fill it completely or nearly completely. This merging approach allows the fabrication equipment to process the combined lot at full processing rate, thereby improving productivity while still maintaining the ability to handle various customer orders and wafer scrub scenarios through the flexible combination of different partial lots.
2Adaptability or versatility
If partial lots are processed separately, then customization for different customer orders is improved, but wait times increase due to repeated setup and processing cycles
Solution Approach 1:
By merging multiple partial lots into a single wafer carrier, the patent reduces the number of separate processing cycles required. This eliminates repeated setup times and carrier handling operations, thereby reducing overall wait times while still accommodating different customer orders through the selective combination of wafers from various partial lots.
3Productivity
If full wafer carriers are used for processing, then productivity and processing rate are improved, but the ability to handle variable lot sizes and customer requirements deteriorates
Solution Approach 1:
The patent segments the wafer carrier filling process into multiple stages: identifying partial lots, selecting compatible lots to combine, and filling the carrier to optimal capacity. This segmentation allows the system to maintain full carrier utilization for high productivity while adapting to variable lot sizes by selectively combining different partial lots to achieve near-full carrier loads.
4Ease of operation
If partially filled wafer carriers are processed, then flexibility in wafer management is improved, but line efficiency deteriorates due to equipment operating below optimal capacity
Solution Approach 1:
The patent merges multiple partial lots into combined lots that fill wafer carriers to full or near-full capacity. This approach maintains the ease of operation regarding wafer management flexibility while dramatically improving line efficiency by ensuring fabrication equipment operates at optimal capacity throughout the processing sequence.
Data Source
AI summary
An integrated circuit is formed by identifying process parameters of a plurality of process steps for the first partial lot containing the integrated circuit; confirming the number of wafers in the first partial lot is less than the wafer carrier capacity; examining lots upstream of the partial lot and identifying a second partial lot which can be combined with the first partial lot into a single wafer carrier and which can be processed with the first partial lot; combining the wafers of the partial lots into a single wafer carrier; processing the partial lots through the plurality of process steps; and performing a multi-lot verification process. The multi-lot verification process determines if all wafers in the partial lots have completed the process step; determines if any wafers in the partial lots are on hold; and determining if all wafers in the partial lots are in a same material carrier.