Wafer Lot Scheduling Under Q-Time Constraints in Semiconductor Fabs

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Solution Overview

Problem

Semiconductor manufacturing processes face challenges in maximizing throughput and minimizing cycle time while adhering to Q-time constraints, which can lead to defective products and decreased productivity due to violations of time limits in processing steps.

Innovation Solution

A Q-time constrained scheduler system that optimizes the delivery of wafer lots to machines using mixed integer linear programming and other optimization techniques, ensuring efficient utilization and compliance with time constraints through operations like simplification of low-utilization steps and dynamic scheduling adjustments.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If traditional scheduling methods are used to maximize throughput, then equipment utilization improves, but Q-time constraints are violated leading to defective products

Engineering Contradiction:
ImprovethroughputVSAvoidQ-time constraint compliance
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The scheduling system dynamically adjusts wafer lot delivery timing based on real-time machine status, queue conditions, and Q-time constraints. The scheduler continuously recalculates optimal delivery times rather than using fixed schedules, allowing the system to adapt to changing conditions while maintaining Q-time compliance and maximizing throughput

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system performs preliminary calculations of Q-time windows and delivery schedules before wafer lots arrive at machines. By pre-computing optimal delivery times and identifying potential Q-time violations in advance, the scheduler can proactively adjust schedules to prevent constraint violations while maintaining high equipment utilization

Inventive Principle:
Principle #10Preliminary action

2Loss of time

If aggressive scheduling is applied to minimize cycle time, then production speed increases, but Q-time violations occur reducing product quality

Engineering Contradiction:
Improvecycle timeVSAvoidproduct quality
Core Design Contradiction:
Loss of timeVSManufacturing precision

Solution Approach 1:

The scheduling system incorporates feedback loops that continuously monitor actual wafer processing times, machine performance, and Q-time compliance. This feedback is used to adjust future delivery schedules, allowing the system to learn from past performance and optimize cycle times while maintaining quality standards through data-driven decision making

Inventive Principle:
Principle #23Feedback

3Ease of operation

If simple scheduling rules are used, then ease of operation improves, but productivity decreases due to suboptimal resource utilization

Engineering Contradiction:
Improvescheduling complexityVSAvoidequipment utilization
Core Design Contradiction:
Ease of operationVSProductivity

Solution Approach 1:

The scheduling system operates autonomously using automated algorithms that calculate optimal wafer lot delivery schedules based on machine capacity, Q-time constraints, and production priorities. The system self-adjusts without manual intervention, maintaining high equipment utilization while simplifying operator workload through automated decision-making

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The scheduler dynamically changes scheduling parameters such as delivery timing, batch sizes, and machine assignment based on real-time conditions. By adjusting these parameters automatically rather than using fixed simple rules, the system achieves high productivity while keeping the user interface simple and easy to operate

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS12451381B2Scheduling multiple production steps under Q-time constraints in semiconductor manufacturing
Publication Date: 2025.10.21 SHI WEIPING
  • US12451381B2 patent drawing
  • US12451381B2 patent drawing
  • US12451381B2 patent drawing

AI summary

A system and method include dividing, by a processor of a manufacturing execution system (MES), a time axis associated with a time window into a plurality of time slots, assigning an integer value to an integer variable indexed by a slot identifier, a machine identifier, and a wafer lot identifier, specifying one or more constraints based on the integer variable, wherein the one or more constraints comprise a wafer quantity constraint and a Q-time constraint, executing an optimization solver under the one or more constraints to determine a time and a quantity of wafer lots to be provided to each machine associated with the time window, and issuing a request to a controller to cause provision of the quantity of wafer lots to each machine associated with each step in the time window.