Wafer Map Classification Using Defect Clusters and ML Features
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Solution Overview
Problem
Current methods for classifying semiconductor wafer maps are inefficient, inaccurate, and not well integrated into manufacturing processes, leading to challenges in identifying patterns of defective dies and improving product quality.
Innovation Solution
An automatic classification framework using clustering analysis and machine learning models to extract global and local features from wafer bin maps, allowing for the identification of defective die patterns and determining the cause of defects in manufacturing processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional manual methods are used for classifying wafer maps, then operators can identify defect patterns, but the process is time-consuming and inefficient
Solution Approach 1:
The patent replaces manual visual inspection and mechanical classification methods with an automated computer-based system that uses machine learning models and image processing algorithms to classify wafer maps, thereby eliminating the time-consuming manual process while maintaining or improving classification accuracy
Solution Approach 2:
The patent introduces an intermediate processing layer that includes feature extraction, image preprocessing, and pattern recognition algorithms between the raw wafer map data and the final classification result, enabling automated analysis without direct human intervention while preserving the ability to identify complex defect patterns
2Measurement precision
If simple classification methods are used, then the process is fast, but accuracy in identifying defect patterns is insufficient
Solution Approach 1:
The patent segments the wafer map classification process into distinct stages including image preprocessing, feature extraction, pattern recognition, and classification decision-making. This segmentation allows each component to be optimized independently, improving overall accuracy while managing system complexity through modular architecture
Solution Approach 2:
The patent transforms the two-dimensional wafer map images into multi-dimensional feature spaces through feature extraction techniques, enabling the machine learning models to capture complex patterns and relationships that would be difficult to detect in the original image space, thereby improving classification accuracy
3Loss of information
If comprehensive feature extraction is performed on all wafer maps, then detailed defect patterns can be identified, but processing time and computational resources increase
Solution Approach 1:
The patent performs preliminary filtering and preprocessing of wafer maps before comprehensive feature extraction, identifying and eliminating obviously defective or normal wafers through quick initial assessments. This preliminary action reduces the number of wafer maps requiring detailed analysis, preserving critical defect information while reducing overall processing time
Solution Approach 2:
The patent applies different levels of feature extraction and analysis to different regions of the wafer map based on local characteristics. Areas with suspected defects receive more detailed analysis while normal regions are processed more quickly, optimizing the balance between information retention and processing efficiency
Data Source
AI summary
A method of testing semiconductor wafers includes receiving a wafer bin map for a semiconductor wafer, wherein the wafer bin map includes a plurality of points corresponding to a plurality of defective dies fabricated on the semiconductor wafer, identifying a cluster of points in the wafer bin map from the plurality of points, and generating a filtered bin map using the cluster of points. The method also includes extracting a set of features for the filtered bin map, wherein the set of features comprises a set of global features common to the semiconductor wafer and a set of cluster features specific to the filtered bin map, executing a trained machine learning model using the set of features as inputs to generate a pattern classification, and determining, based on the pattern classification, that the semiconductor wafer includes a pattern of defective dies caused by a defective manufacturing process.