Wafer Map Display Links DUTs to Tester LSIs
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Solution Overview
Problem
Current semiconductor wafer inspection systems lack the ability to quickly analyze and predict tester failures, leading to prolonged downtime due to the absence of a method for predicting tester failures before they occur.
Innovation Solution
An inspection system with a wafer map display application that links display portions for DUTs on a semiconductor wafer map to corresponding LSIs on tester module boards, allowing for the visualization of inspection and self-diagnosis results, enabling quick identification and prediction of tester failures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If traditional inspection systems display only PASS/NG results on wafer maps, then the display is simple and easy to understand, but the time required for failure analysis is prolonged because tester failure locations cannot be identified
Solution Approach 1:
The patent embeds tester module board information and LSI information within the wafer map display structure. Each DUT display portion contains nested information about the corresponding tester module board and LSI, allowing failure location identification without adding separate complex display systems. The wafer map becomes a multi-layered information container that reveals tester status at different levels of zoom or interaction.
Solution Approach 2:
The patent adds a new dimension to the traditional wafer map by incorporating tester module board and LSI identification information. This transforms the display from a two-dimensional PASS/NG result map into a multi-dimensional diagnostic tool that includes spatial information about tester components, enabling failure location identification while maintaining the familiar wafer map interface.
2Productivity
If no failure prediction capability is implemented, then the system is simpler to operate, but apparatus downtime increases when tester failures occur
Solution Approach 1:
The patent displays self-diagnosis results alongside inspection results on the wafer map, enabling operators to identify potential tester failures before they cause apparatus downtime. By showing tester status information in advance through the same interface, the system allows proactive maintenance actions without adding complex separate monitoring systems.
Solution Approach 2:
The patent implements a feedback mechanism where self-diagnosis results from tester components are continuously monitored and displayed on the wafer map. This feedback loop provides real-time information about tester health status, allowing operators to take corrective action before failures occur, thereby improving apparatus uptime while maintaining operational simplicity.
Data Source
AI summary
An inspection system is provided with a prober and a tester. The tester includes a plurality of tester module boards on which a plurality of LSIs respectively corresponding to a plurality of devices under test (DUT) are mounted; a display unit which displays a wafer map indicating inspection results of the plurality of DUTs and/or self-diagnosis results of the tester; and a tester control unit which includes a wafer map drawing application for drawing the wafer map displayed on the display unit. The wafer map drawing application causes the inspection results and/or the self-diagnosis results to be displayed for each of the plurality of DUTs in a stepwise manner. In the wafer map, the plurality of DUTs are respectively linked to correspond to the plurality of LSIs mounted on the plurality of tester module boards.