Wafer Map Edge Analysis for Random vs Systematic Chip Failures
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Solution Overview
Problem
Existing methods for identifying semiconductor chip failures on wafers, particularly at the edge, suffer from low yield accuracy due to difficulties in distinguishing between random and systematic failures, leading to inefficient process improvements.
Innovation Solution
A method and device that analyze wafer maps by counting adjacent normal or defective chips to determine whether failures are random or systematic, using virtual normal chips at the edge to ensure consistent analysis, and adjusting failure classifications based on predetermined criteria.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If virtual normal chips are applied at the wafer edge to ensure consistent analysis, then measurement precision is improved, but device complexity increases
Solution Approach 1:
Virtual normal chips are applied to the wafer map before failure analysis to pre-establish consistent boundary conditions. This preliminary action ensures that edge chips have the same number of adjacent chips (eight) as interior chips, enabling uniform failure type determination across the entire wafer surface and improving measurement precision.
Solution Approach 2:
Virtual normal chips act as intermediary elements that mediate between the physical wafer edge and the analysis requirements. These virtual chips provide the missing adjacent chip information for edge chips, allowing the same failure determination logic to be applied uniformly without requiring special edge-case handling.
2Device complexity
If failure identification is performed without virtual chips at the edge, then device complexity is reduced, but measurement precision deteriorates due to insufficient adjacent chip data
Solution Approach 1:
The wafer map is pre-modified by applying virtual normal chips to edge positions before conducting failure analysis. This ensures that all chips, including edge chips, have complete adjacent chip data (eight neighbors), eliminating data insufficiency issues and improving measurement precision without complicating the analysis process.
Solution Approach 2:
Virtual normal chips are selectively applied only at the wafer edge positions where data is insufficient, rather than modifying the entire wafer map uniformly. This localized application provides the necessary adjacent chip information exactly where needed while maintaining the original chip configuration in the interior regions.
Data Source
AI summary
An operation method of a wafer analysis device include: generating a wafer map that is an image visualizing and showing whether each of a plurality of chips included in a wafer is normal or defective; applying virtual normal chips to the wafer map such that the number of chips adjacent to each of all the chips on an outermost edge of the wafer map is eight; obtaining the number of normal chips among eight adjacent chips of each of defective chips among the plurality of chips; determining whether a failure of each of the defective chips is caused by a systematic failure or a random failure.