Wafer Map Analysis Using Inception Module and Shortcut Connections
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Solution Overview
Problem
In the semiconductor manufacturing environment, the complexity of wafer maps and limited computing resources pose a challenge for efficiently processing and accurately classifying defect types using neural networks, leading to increased computational demands.
Innovation Solution
A wafer map analysis system and method utilizing a neural network with an inception module and shortcut connections to process wafer maps efficiently, including pre-processing, feature extraction, and defect type determination, optimizing computational resources and improving learning performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional neural networks are used to classify complex wafer map patterns, then classification accuracy can be maintained, but computational complexity and resource requirements increase dramatically
Solution Approach 1:
The neural network is divided into multiple stages: a first neural network performs initial defect detection and classification on the wafer map, and a second neural network performs detailed analysis only on detected defect regions. This segmentation allows the system to maintain high classification accuracy while reducing overall computational complexity by avoiding full-network processing of entire wafer maps.
Solution Approach 2:
The system applies partial processing by using the first neural network to identify and classify defects across the entire wafer map, then applying the computationally intensive second neural network only to specific defect regions of interest. This partial action approach maintains accuracy for critical defects while significantly reducing total computational requirements compared to processing the entire map with a complex network.
2Measurement precision
If complex neural network architectures are deployed to handle diverse defect patterns, then defect detection accuracy improves, but processing speed decreases
Solution Approach 1:
The processing pipeline is segmented into two phases: rapid initial screening using the first neural network that identifies potential defect locations, followed by detailed analysis using the second neural network only on confirmed defect regions. This segmentation enables the system to achieve high detection accuracy while maintaining processing speed by avoiding exhaustive complex analysis of every region of the wafer map.
Solution Approach 2:
The system performs partial detailed analysis only on regions where defects are detected by the first neural network, rather than applying the full computational power of complex architectures to the entire wafer map. This partial action maintains high detection accuracy for actual defects while significantly improving processing speed by skipping unnecessary computations in defect-free regions.
3Measurement precision
If comprehensive feature extraction is performed to capture all defect characteristics, then classification precision improves, but computational resource consumption increases
Solution Approach 1:
Feature extraction is segmented into two levels: the first neural network extracts basic defect features and performs initial classification, while the second neural network extracts detailed characteristic features only for defects that require further analysis. This segmentation allows the system to maintain high classification precision for all defects while reducing computational resource consumption by performing comprehensive feature extraction only when necessary.
Solution Approach 2:
The system performs comprehensive feature extraction partially - only for defect regions identified by the first neural network - rather than extracting all possible features from the entire wafer map. This partial comprehensive extraction maintains high classification precision for detected defects while significantly reducing computational resource consumption compared to exhaustive feature extraction across the full map.
Data Source
AI summary
A method of analyzing a wafer map using a neural network and a wafer map analysis system are provided. The method of analyzing a wafer map using a neural network includes creating a wafer map based on raw data, receiving, by an inception module including a plurality of inception layers, a first output feature map created based on the wafer map, outputting, by the inception module, a final inception output feature map based on the first output feature map, connecting the first output feature map to the final inception output feature map through a shortcut connection, and performing an addition operation on the first output feature map and the final inception output feature map to output a second output feature map.