Wafer Map Spatial Filtering for Localized Failure Detection
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Solution Overview
Problem
Conventional wafer level testing methods are inadequate in identifying localized failures on semiconductor chips, providing only lot-by-lot information and failing to distinguish between distributed and localized failure modes, which limits the efficiency of yield improvement efforts.
Innovation Solution
A method and system that generate a wafer map, apply a spatial filter to identify localized failures, calculate a defect index value, and compare it to a critical upper limit to determine wafer defectiveness on a per-wafer basis, enabling real-time identification of defective wafers within a fabrication lot.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional wafer level testing methods are used, then lot-by-lot information is provided, but the ability to identify localized failures is insufficient
Solution Approach 1:
The patent segments the wafer into multiple zones and applies spatial filtering to identify localized failure patterns within specific regions. By dividing the wafer map into manageable segments and analyzing each independently, the system can detect localized failures that would be obscured in aggregate lot-by-lot data.
Solution Approach 2:
The patent introduces spatial dimensionality to the failure analysis by examining the physical location and distribution of failures across the wafer surface. Instead of treating all failures equally regardless of location, the system analyzes spatial patterns and coordinates to identify localized failure clusters, adding a geographic dimension to the detection process.
2Productivity
If conventional testing provides only lot-by-lot information, then resource allocation is inefficient, but detailed per-wafer analysis is not available
Solution Approach 1:
The patent performs preliminary spatial analysis and defect indexing at the wafer level before package-level testing. By pre-identifying wafers with localized failure patterns and calculating defect indices in advance, the system prepares targeted information that accelerates subsequent failure analysis and reduces the time needed for detailed investigation.
Solution Approach 2:
The system establishes a feedback loop where wafer-level spatial analysis results inform package-level testing strategies. The defect index values and localized failure identification provide feedback that guides resource allocation and prioritization, enabling more efficient failure analysis by focusing on high-risk wafers first.
3Reliability
If distributed and localized failure modes are not distinguished, then yield metrics are inaccurate, but the testing process remains simple
Solution Approach 1:
The patent applies local quality analysis by examining failure patterns in specific local regions of the wafer rather than treating the entire wafer uniformly. By calculating defect indices for localized zones and comparing them against thresholds, the system can distinguish between distributed random failures and localized systematic failures, providing more accurate yield metrics that reflect actual failure modes.
Data Source
AI summary
A method and system for testing a wafer comprising semiconductor chips are disclosed. A determination of whether or not the wafer is defective is made in relation to a spatially related group of filtered failed semiconductor chips on the wafer, where the spatially related group corresponds to a localized failure on the wafer and is used to calculate a defect index value.