Wafer Map Based Test Condition Determination for Semiconductor Epitaxial Layers

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Solution Overview

Problem

Existing techniques for testing semiconductor elements with epitaxial growth layers fail to determine appropriate test conditions, leading to potential damage of semiconductor elements, electrodes, and probes due to excessive crystal defects, which can result in decreased withstand voltage and equipment damage.

Innovation Solution

A test condition determining apparatus comprising a map generating unit, a withstand voltage estimating unit, and a test condition determining unit that generates a wafer map based on thickness, carrier concentration, and crystal defect measurements to estimate withstand voltage and determine appropriate test conditions for each chip, preventing damage during testing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If withstand voltage test is conducted with maximum rating value on semiconductor element with high crystal defects, then test coverage is improved, but semiconductor element and equipment may be damaged

Engineering Contradiction:

Improvetest coverageVSAvoiddamage to semiconductor element, electrode, or probe

Core Design Contradiction:

ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent performs preliminary measurement of crystal defects in the epitaxial growth layer and substrate before conducting withstand voltage tests. Based on these measurements, the test voltage is predetermined and adjusted for each chip location, allowing safe testing conditions to be established in advance and preventing damage during actual testing.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent determines test conditions locally for each chip based on the specific crystal defect characteristics at that location. The withstand voltage test condition is adjusted according to the measured crystal defect density in each region, allowing optimized testing that adapts to local variations in quality across the semiconductor wafer.

Inventive Principle:

Principle #3Local quality

2Ease of operation

If uniform test condition is applied to all chips, then testing process is simplified, but chips with low withstand voltage may be damaged

Engineering Contradiction:

Improvetesting process simplicityVSAvoidchip safety

Core Design Contradiction:

Ease of operationVSReliability

Solution Approach 1:

The patent divides the semiconductor wafer into multiple regions based on crystal defect density measurements. Each region is assigned different test voltage levels according to its quality characteristics, transforming a uniform testing approach into a segmented, location-specific testing strategy that prevents damage while maintaining operational efficiency.

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS10886184B2Test condition determining apparatus and test condition determining method

Publication Date: 2021.01.05 MITSUBISHI ELECTRIC CORP

AI summary

The object is to provide a technique for enabling determination of an appropriate test condition. A test condition determining apparatus includes a map generating unit, a withstand voltage estimating unit, and a test condition determining unit. The map generating unit generates a wafer map relevant to a plurality of chips, based on measurement values of thicknesses and carrier concentrations of an epitaxial growth layer, and measurement results of crystal defects in the epitaxial growth layer and a substrate. The withstand voltage estimating unit estimates a withstand voltage of each of the chips based on the wafer map. The test condition determining unit determines a test condition of a test to be conducted on the chips, based on a result of the estimation made by the withstand voltage estimating unit.