Wafer Marking Region Planarization via Dielectric Layer
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Solution Overview
Problem
The existing methods for creating machine-readable identification markings on semiconductor wafers often introduce surface roughness and debris, leading to reduced planarity and increased defectivity during processing, which negatively impacts the yield of integrated circuit fabrication.
Innovation Solution
A structure and method involving a dielectric layer with a planarized top surface are used to cover both the metal wiring region and the marking region on the wafer, where the identification marking is formed, ensuring that the surface is smooth and free of topography issues, thereby improving planarity and reducing defectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of information
If a laser scribe is used to form an identification marking on the wafer, then the wafer can be identified during processing, but surface roughness and debris are introduced that reduce planarity and increase defectivity
Solution Approach 1:
A dielectric layer is deposited over the laser-scribed marking region to act as an intermediary that covers the surface roughness and debris. This dielectric layer serves as a mediator between the marked surface and subsequent processing steps, preventing the roughness from affecting planarity requirements while preserving the identification marking underneath.
Solution Approach 2:
The dielectric layer functions as a sacrificial or temporary structure that can be removed or planarized if needed. It provides a low-cost solution to mask surface defects without requiring complex repair processes, and can be discarded or modified in subsequent fabrication steps.
2Loss of information
If a laser scribe is used to create the identification marking, then the marking is formed, but debris is produced that reduces yield
Solution Approach 1:
The dielectric layer acts as a protective intermediary that encapsulates the debris and roughness artifacts generated during laser scribing. By covering these harmful byproducts, the dielectric prevents them from causing defects in subsequent processing steps, thereby maintaining high fabrication yield while preserving the identification marking.
3Loss of information
If the wafer surface is altered to form the marking, then the identification is created, but planarity is reduced affecting subsequent processing
Solution Approach 1:
The dielectric layer serves as a planarizing intermediary that provides a smooth upper surface for subsequent fabrication steps. It decouples the marking formation process (which creates roughness) from the subsequent processing requirements (which need planarity), allowing both to coexist without conflict.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The planarized dielectric layer enhances the surface uniformity, reduces defectivity, and improves the bonding process, leading to higher yields and reduced risk of delamination or cracking during subsequent wafer processing and bonding steps.
Implementation Method 1
The wafer identification marking is commonly transferred to a front side of the wafer in a 'clear cell' marking region using a laser scribe. The laser scribing process alters the surface topography to construct characters or symbols representing the identification marking.
Implementation Method 2
a dielectric layer is deposited on the marking region and the metal wiring region
Implementation Method 3
The dielectric layer has a planarized top surface
Data Source
AI summary
Structures that include an identification marking and fabrication methods for such structures. A chip is formed within a usable area of a wafer, and a marking region is formed on the wafer. The marking region is comprised of a conductor used to form a last metal layer of an interconnect structure for the chip. The identification marking is formed in the conductor of the marking region. After the identification marking is formed, a dielectric layer is deposited on the marking region. The dielectric layer on the marking region is planarized.