Wafer-on-Wafer Memory Latency Control for Blockchain Servers
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Solution Overview
Problem
Blockchain server hardware architecture struggles to adapt to frequent changes in blockchain algorithms, requiring flexible parameter adjustments to maintain optimal performance and efficiency.
Innovation Solution
A computer system utilizing wafer-on-wafer technology with a three-dimensional structural configuration, where memory devices and logic circuits are stacked, allowing for dynamic adjustment of memory array dimensions through multiplexers and line drivers to optimize latency and data transmission performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional planar memory architecture is used, then manufacturing is simpler, but data transmission performance and latency are insufficient
Solution Approach 1:
The patent transitions from a traditional planar (2D) memory architecture to a three-dimensional stacked architecture. Multiple memory wafers are vertically stacked and bonded together, creating a 3D structure that increases data transmission capacity and reduces latency by providing multiple parallel transmission paths through the vertical dimension, thereby resolving the contradiction between transmission performance and architectural complexity.
Solution Approach 2:
The memory system is segmented into multiple independent wafers that are stacked vertically. Each wafer contains separate memory arrays and can be independently controlled through the latency controller. This segmentation allows parallel access to different memory regions, improving data transmission speed while maintaining manageable complexity through modular design.
2Adaptability or versatility
If fixed memory array dimensions are used, then device structure is simpler, but adaptability to changing blockchain algorithms is reduced
Solution Approach 1:
The patent introduces a latency controller that dynamically reconfigures the memory array dimensions by controlling multiplexers. The controller can adjust the number of rows and columns accessible in each memory array based on the specific blockchain algorithm requirements, transforming a static memory structure into a dynamic one that adapts to different computational tasks while managing complexity through software-controlled configuration.
Solution Approach 2:
The memory system is designed with universal functionality to support multiple blockchain algorithms by allowing flexible reconfiguration of memory array dimensions. The same physical memory structure can be adapted to serve different algorithmic requirements through the latency controller and multiplexer configuration, eliminating the need for hardware changes when algorithms evolve.
3Quantity of substance
If more transmission lines are added in planar design, then data transmission capacity increases, but area consumption and manufacturing complexity increase
Solution Approach 1:
The patent utilizes the vertical dimension by stacking multiple memory wafers together, allowing transmission lines to be distributed across different vertical layers. This 3D arrangement enables a high density of transmission lines without proportionally increasing the horizontal wafer area, as lines from different wafers occupy the same planar footprint but are separated vertically through bonding interfaces.
Data Source
AI summary
A computer system based on wafer-on-wafer architecture is provided, comprising a memory device and a logic circuit layer stacked in a wafer on wafer structural configuration. The memory device comprises a memory array and a circuit driver. The memory array comprises a shared circuit path and a plurality of memory cells, wherein the shared circuit path is connected to the memory cells. The circuit driver is connected to the shared circuit path, driving the memory cells. The logic circuit layer comprises a plurality of bonding pads for signal transmission, and a latency controller, connected to the memory array through the bonding pads, adjusting the number of memory cells connecting the shared circuit path, thereby dynamically adjusting the latency characteristics of the memory array. Embodiments of the memory device and the memory control method are also provided.