Wafer-on-Wafer Memory-Logic I/O Bonding for Dense High-Bandwidth Links
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Solution Overview
Problem
Existing manufacturing processes for 3D ICs, such as wafer-on-wafer bonding, are expensive and time-consuming due to complex alignment and bonding operations, limiting the efficiency and scalability of memory and logic devices.
Innovation Solution
A wafer-on-wafer bonding process that directly couples global input/output lines of memory and logic devices, forming a hybrid bond for efficient data transmission and reducing electrical resistance, allowing for a face-to-face arrangement that increases connection density and bandwidth within a fixed power envelope.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If wafer-on-wafer bonding is used to couple memory and logic devices, then bandwidth and connection density are improved, but manufacturing cost and process time increase
Solution Approach 1:
The patent applies preliminary action by pre-forming protrusions on one wafer and recesses on the other wafer before the bonding process. These pre-formed features guide the alignment and coupling process, making the subsequent bonding operation simpler and more efficient. The protrusions and recesses are created during separate wafer fabrication steps, so the complex alignment structure is prepared in advance rather than during the time-critical bonding process itself.
Solution Approach 2:
The patent introduces an intermediary mechanism in the form of complementary protrusions and recesses that mediate the coupling between wafers. These features act as mechanical guides and alignment aids, translating the complex alignment requirement into a simpler fit-between-parts operation. The protrusions fit into the recesses to provide both mechanical support and electrical connection pathways, simplifying the overall coupling process.
2Quantity of substance
If wafer-on-wafer bonding is used to couple memory and logic devices, then connection density and bandwidth are improved, but alignment complexity and process time increase
Solution Approach 1:
The alignment features (protrusions and recesses) are prepared in advance during separate wafer fabrication steps, converting the complex alignment problem into a pre-solved geometric matching problem. This preliminary preparation eliminates the need for complex real-time alignment procedures during bonding.
Solution Approach 2:
The protrusions and recesses serve as intermediary alignment features that mediate the coupling process. By providing fixed geometric reference points, they transform the complex multi-degree-of-freedom alignment problem into a simple insertion operation where the protrusion naturally guides into the matching recess, automatically establishing correct relative positioning.
3Reliability
If direct coupling of global input/output lines is implemented, then electrical resistance is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The electrical connection pathways are prepared in advance as integrated structures within the wafer layers. The conductive paths extending from the global input/output lines to the bonding interface are formed during standard fabrication processes, ensuring their precision and reliability before the coupling operation occurs.
Solution Approach 2:
The protrusions and recesses serve as intermediary structures that provide both mechanical support and electrical connectivity. By integrating the electrical pathways within these structural features, the patent simultaneously addresses mechanical alignment and electrical connection requirements, reducing the need for separate high-precision bonding operations for each function.
Data Source
AI summary
A wafer-on-wafer bonded memory and logic device can enable high bandwidth transmission of data directly between a memory die and a logic die. A memory device formed on a memory die can include many global input/output lines and many arrays of memory cells. Each array of memory cells can include respective local input/output (LIO) lines coupled to a global input/output line. A logic device can be formed on a logic die. A bond, formed between the memory die and the logic die via a wafer-on-wafer bonding process, can couple the many global input/output lines to the logic device.