Wafer-on-Wafer Memory Testing Before 3D Bonding
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Solution Overview
Problem
The wafer-on-wafer bonding process in manufacturing 3D ICs poses challenges in accessing and testing components after bonding, as they become covered or surrounded, making it difficult to determine the functionality and suitability of memory devices before further processing.
Innovation Solution
Forming contacts on wafers coupled to memory devices for testing before bonding, allowing pre-bonding evaluation and enabling efficient alignment and bonding operations, which are then removed before the final wafer-on-wafer bonding process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If wafer-on-wafer bonding is performed to create 3D ICs, then integration density and bandwidth are improved, but accessibility for testing memory devices is lost
Solution Approach 1:
The patent applies preliminary action by performing memory device testing on the first wafer before the wafer-on-wafer bonding process. Test structures are formed and memory devices are tested while still accessible on the separate wafer, allowing functional verification before integration. This prevents the loss of testing accessibility that would occur after bonding, as the testing is completed in advance when components are still accessible.
2Reliability
If wafer-on-wafer bonding is performed, then device functionality is improved through tight coupling, but component accessibility for evaluation is reduced
Solution Approach 1:
The patent implements preliminary action by evaluating memory device functionality and performance before the bonding process. Memory devices are tested, characterized, and evaluated on the first wafer while accessible, allowing selection of suitable devices for integration. This ensures device functionality is verified in advance, and the bonding process then creates the tight coupling for improved reliability without compromising the ability to evaluate components beforehand.
3Reliability
If testing is performed after wafer bonding, then integrated system functionality can be verified, but testing complexity and difficulty increase
Solution Approach 1:
The patent applies segmentation by dividing the testing process into separate stages: first wafer testing before bonding, and post-bonding verification. Memory devices are tested individually on the first wafer using test structures formed on that wafer, simplifying the testing process. After bonding, only final system verification is needed. This segmentation reduces testing complexity compared to attempting to test all components after bonding, as initial testing is performed when devices are more accessible and can be tested in isolation.
Data Source
AI summary
A wafer-on-wafer bonded memory and logic device can enable high bandwidth transmission of data directly between a memory die and a logic die. Memory devices can be formed on a first wafer. First metal pads can be formed on the first wafer and coupled to the memory devices. The memory devices can be tested via the first metal pads. The first metal pads can be removed from the first wafer. Subsequently, second metal pads on the first wafer can be bonded, via a wafer-on-wafer bonding process, to third metal pads on a second wafer. Each memory device on the first wafer can be aligned with and coupled to a respective logic device on the second wafer.